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AD7888BR-REEL Datenblatt(PDF) 10 Page - Analog Devices |
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AD7888BR-REEL Datenblatt(HTML) 10 Page - Analog Devices |
10 / 17 page AD7888 –10– order to obtain optimum performance from the device it is advised to disable the internal reference by setting the REF bit in the Control Register when an external reference is applied. When the internal reference is disabled, SW1 in Figure 11 will open and the input impedance seen at the REF IN/REF OUT pin is the input impedance of the reference buffer, which is in the region of giga Ω. When the reference is enabled, the input impedance seen at the pin is typically 5 k Ω. SW1 5k 2.5V REF IN/REF OUT Figure 11. On-Chip Reference Circuitry Table III. Power Management Options PM1 PM0 Mode 00 Normal Operation. In this mode, the AD7888 remains in full power mode regardless of the status of any of the logic inputs. This mode allows the fastest possible throughput rate from the AD7888. 01 Full Shutdown. In this mode, the AD7888 is in full shutdown mode with all circuitry on the AD7888, including the on-chip reference, enter- ing its power-down mode. The AD7888 retains the information in the control Register bits while in full shutdown. The part remains in full shutdown until these bits are changed. 10 Autoshutdown. In this mode, the AD7888 automatically enters full shutdown mode at the end of each conversion. Wake-up time from full shutdown is 5 µs and the user should ensure that 5 µs have elapsed before attempting to perform a valid conversion on the part in this mode. 11 Autostandby. In this standby mode, portions of the AD7888 are powered down but the on- chip reference voltage remains powered up. The REF bit should be 0 to ensure the on-chip refer- ence is enabled. This mode is similar to auto- shutdown but allows the part to power-up much faster. POWER-DOWN OPTIONS The AD7888 provides flexible power management to allow the user to achieve the best power performance for a given through- put rate. The power management options are selected by programming the power management bits (i.e., PM1 and PM0) in the control register. Table III summarizes the options available. When the power management bits are programmed for either of the auto power-down modes, the part will enter the power-down mode on the 16th rising SCLK edge after the falling edge of CS. The first falling SCLK edge after the CS falling edge will cause the part to power up again. When the AD7888 is in full shutdown, the only way to fully power it up again is to reprogram the power management bits to PM1 = PM0 = 0, i.e., normal mode. In this case the device will power up on the 16th SCLK rising edge after the CS falling edge as this is when the power management bits become effective. Power-Up Times The AD7888 has an approximate 1 µs power-up time when powering up from standby or when using an external reference. When VDD is first connected, the AD7888 will fully power up, i.e., it powers up in normal mode. If the part is put into shut- down, a subsequent power-up will take approximately 5 µs. The AD7888 wake-up time is very short in the autostandby mode so it is possible to wake up the part and carry out a valid conver- sion in the same read/write operation. POWER vs. THROUGHPUT RATE By operating the AD7888 in autoshutdown or autostandby mode the average power consumption of the AD7888 decreases at lower throughput rates. Figure 12 shows how as the through- put rate is reduced, the device remains in its power-down state longer and the average power consumption over time drops accordingly. For example, if the AD7888 were operated in a continuous sampling mode, with a throughput rate of 10 kSPS and a SCLK of 2 MHz (VDD = 5 V), and if PM1 = 1 and PM0 = 0, i.e., the device is in autoshutdown mode and the on-chip reference is used, the power consumption is calculated as follows. The power dissipation during normal operation is 3.5 mW (VDD = 5 V). If the power-up time is 5 µs and the remaining conversion- plus-acquisition time is 15.5 tSCLK, i.e., approximately 7.75 µs, (see Figure 14a), the AD7888 can be said to dissipate 3.5 mW for 12.75 µs during each conversion cycle. If the throughput rate is 10 kSPS, the cycle time is 100 µs and the average power dissi- pated during each cycle is (12.75/100) × (3.5 mW) = 446.25 µW. If VDD = 3 V SCLK = 2 MHz, and the device is again in auto- shutdown mode using the on-chip reference, the power dissipa- tion during normal operation is 2.1 mW. The AD7888 can now be said to dissipate 2.1 mW for 12.75 µs during each conversion cycle. With a throughput rate of 10 kSPS, the average power dissipated during each cycle is (12.75/100) × (2.1 mW) = 267.75 µW. Figure 12 shows the power vs. throughput rate for automatic shutdown with both 5 V and 3 V supplies. THROUGHPUT – kSPS 10 0 1 10 0.1 0.01 VDD = 5V SCLK = 2MHz VDD = 3V SCLK = 2MHz 20 30 40 50 Figure 12. Power vs. Throughput REV. C |
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Ähnliche Beschreibung - AD7888BR-REEL |
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