Datenblatt-Suchmaschine für elektronische Bauteile
  German  ▼
ALLDATASHEETDE.COM

X  

AD7710AQ Datenblatt(PDF) 5 Page - Analog Devices

Teilenummer AD7710AQ
Bauteilbeschribung  Signal Conditioning ADC
Download  32 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Hersteller  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7710AQ Datenblatt(HTML) 5 Page - Analog Devices

  AD7710AQ Datasheet HTML 1Page - Analog Devices AD7710AQ Datasheet HTML 2Page - Analog Devices AD7710AQ Datasheet HTML 3Page - Analog Devices AD7710AQ Datasheet HTML 4Page - Analog Devices AD7710AQ Datasheet HTML 5Page - Analog Devices AD7710AQ Datasheet HTML 6Page - Analog Devices AD7710AQ Datasheet HTML 7Page - Analog Devices AD7710AQ Datasheet HTML 8Page - Analog Devices AD7710AQ Datasheet HTML 9Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 5 / 32 page
background image
AD7710
REV. G
–5–
(DVDD = +5 V
5%; AVDD = +5 V or +10 V
3
5%; VSS = 0 V or –5 V
10%; AGND = DGND =
0 V; fCLK IN =10 MHz; Input Logic 0 = 0 V, Logic 1 = DVDD, unless otherwise noted.)
TIMING CHARACTERISTICS1, 2
Limit at TMIN, TMAX
Parameter
(A, S Versions)
Unit
Conditions/Comments
fCLK IN
4, 5
Master Clock Frequency: Crystal Oscillator or Externally
400
kHz min
Supplied for Specified Performance
10
MHz max
AVDD = +5 V
± 5%
8
MHz max
AVDD = +5.25 V to +10.5 V
tCLK IN LO
0.4
× t
CLK IN
ns min
Master Clock Input Low Time. tCLK IN = 1/fCLK IN
tCLK IN HI
0.4
× t
CLK IN
ns min
Master Clock Input High Time
tr
6
50
ns max
Digital Output Rise Time. Typically 20 ns
tf
6
50
ns max
Digital Output Fall Time. Typically 20 ns
t1
1000
ns min
SYNC Pulse Width
Self-Clocking Mode
t2
0
ns min
DRDY to RFS Setup Time
t3
0
ns min
DRDY to RFS Hold Time
t4
2
× tCLK IN
ns min
A0 to
RFS Setup Time
t5
0
ns min
A0 to
RFS Hold Time
t6
4
× t
CLK IN + 20
ns max
RFS Low to SCLK Falling Edge
t7
7
4
× tCLK IN + 20
ns max
Data Access Time (
RFS Low to Data Valid)
t8
7
tCLK IN/2
ns min
SCLK Falling Edge to Data Valid Delay
tCLK IN/2 + 30
ns max
t9
tCLK IN/2
ns nom
SCLK High Pulse Width
t10
3
× t
CLK IN/2
ns nom
SCLK Low Pulse Width
t14
50
ns min
A0 to
TFS Setup Time
t15
0
ns min
A0 to
TFS Hold Time
t16
4
× t
CLK IN + 20
ns max
TFS to SCLK Falling Edge Delay Time
t17
4
× t
CLK IN
ns min
TFS to SCLK Falling Edge Hold Time
t18
0
ns min
Data Valid to SCLK Setup Time
t19
10
ns min
Data Valid to SCLK Hold Time
NOTES
1Guaranteed by design, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2See Figures 10 to 13.
3The AD7710 is specified with a 10 MHz clock for AV
DD voltages of 5 V
± 5%. It is specified with an 8 MHz clock for AV
DD voltages greater than 5.25 V and less
than 10.5 V.
4CLK IN duty cycle range is 45% to 55%. CLK IN must be supplied whenever the AD7710 is not in STANDBY mode. If no clock is present in this case, the device
can draw higher current than specified and possibly become uncalibrated.
5The AD7710 is production tested with f
CLK IN at 10 MHz (8 MHz for AVDD > 5.25 V). It is guaranteed by characterization to operate at 400 kHz.
6Specified using 10% and 90% points on waveform of interest.
7These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
ORDERING GUIDE
Temperature
Package
Model
1
Range
Options
2
AD7710AN
–40
°C to +85°C
N-24
AD7710AR
–40
°C to +85°C
R-24
AD7710AR-REEL
–40
°C to +85°C
R-24
AD7710AR-REEL7
–40
°C to +85°C
R-24
AD7710ARZ
3
–40
°C to +85°C
R-24
AD7710ARZ-REEL
3
–40
°C to +85°C
R-24
AD7710ARZ-REEL7
3
–40
°C to +85°C
R-24
AD7710AQ
–40
°C to +85°C
Q-24
AD7710SQ
–55
°C to +125°C
Q-24
EVAL-AD7710EB
Evaluation Board
NOTES
1Contact your local sales office for military data sheet and availability.
2N = PDIP; Q = CERDIP; R = SOIC.
3Z = Pb-free part.


Ähnliche Teilenummer - AD7710AQ

HerstellerTeilenummerDatenblattBauteilbeschribung
logo
Analog Devices
AD7710AQ AD-AD7710AQ Datasheet
220Kb / 28P
   Signal Conditioning ADC
REV. F
More results

Ähnliche Beschreibung - AD7710AQ

HerstellerTeilenummerDatenblattBauteilbeschribung
logo
Analog Devices
AD7712 AD-AD7712_15 Datasheet
258Kb / 28P
   Signal Conditioning ADC
REV. F
AD7711 AD-AD7711_17 Datasheet
354Kb / 29P
   Signal Conditioning ADC
AD7714 AD-AD7714_17 Datasheet
349Kb / 41P
   Signal Conditioning ADC
AD7710 AD-AD7710 Datasheet
220Kb / 28P
   Signal Conditioning ADC
REV. F
AD7710ANZ AD-AD7710ANZ Datasheet
265Kb / 32P
   Signal Conditioning ADC
REV. G
AD7712 AD-AD7712_17 Datasheet
304Kb / 29P
   Signal Conditioning ADC
AD7710 AD-AD7710_17 Datasheet
319Kb / 33P
   Signal Conditioning ADC
AD7714 AD-AD7714_15 Datasheet
298Kb / 40P
   Signal Conditioning ADC
REV. C
AD7710 AD-AD7710_15 Datasheet
265Kb / 32P
   Signal Conditioning ADC
REV. G
AD7712 AD-AD7712 Datasheet
229Kb / 28P
   LC2MOS Signal Conditioning ADC
REV. E
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32


Datenblatt Download

Go To PDF Page


Link URL




Privatsphäre und Datenschutz
ALLDATASHEETDE.COM
War ALLDATASHEET hilfreich?  [ DONATE ] 

Über Alldatasheet   |   Werbung   |   Kontakt   |   Privatsphäre und Datenschutz   |   Linktausch   |   Hersteller
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com