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ADN2817ACPZ Datenblatt(PDF) 6 Page - Analog Devices |
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ADN2817ACPZ Datenblatt(HTML) 6 Page - Analog Devices |
6 / 40 page ADN2817/ADN2818 Data Sheet Rev. E | Page 6 of 40 OUTPUT AND TIMING SPECIFICATIONS Table 3. Parameter Conditions Min Typ Max Unit CML OUPUT CHARACTERISTICS (CLKOUTP/CLKOUTN, DATAOUTP/DATAOUTN) Single-Ended Output Swing, VSE See Figure 3 300 350 600 mV Differential Output Swing, VDIFF See Figure 3 600 700 1200 mV Output Voltage High, VOH VCC V Low, VOL VCC − 0.6 VCC − 0.35 VCC − 0.3 V CML Outputs Timing Rise Time 20% to 80% 80 112 ps Fall Time 80% to 20% 80 123 ps Setup Time, tS See Figure 2, OC-48 150 200 250 ps Hold Time, tH See Figure 2, OC-48 150 200 250 ps Setup Time, tDDRS See Figure 4, OC-48 140 170 200 ps Hold Time, tDDRH See Figure 4, OC-48 200 230 260 ps I2C INTERFACE DC CHARACTERISTICS LVCMOS Input Voltage High, VIH 0.7 VCC V Low, VIL 0.3 VCC V Input Current VIN = 0.1 VCC or VIN = 0.9 VCC −10.0 +10.0 µA Output Low Voltage VOL, IOL = 3.0 mA 0.4 V I2C INTERFACE TIMING See Figure 22 SCK Clock Frequency 400 kHz SCK Pulse Width High High, tHIGH 600 ns Low, tLOW 1300 ns Start Condition Hold Time, tHD;STA 600 ns Setup Time, tSU;STA 600 ns Data Setup Time, tSU;DAT 100 ns Hold Time, tHD;DAT 300 ns SCK/SDA Rise/Fall Time, tR/tF 20 + 0.1 Cb 300 ns Stop Condition Setup Time, tSU;STO 600 ns Bus Free Time Between a Stop and a Start, tBUF 1300 ns REFCLK CHARACTERISTICS Optional lock to REFCLK mode Input Voltage Range At REFCLKP or REFCLKN VIL 0 V VIH VCC V Minimum Differential Input Drive 100 mV p-p Reference Frequency 10 200 MHz Required Accuracy 100 ppm |
Ähnliche Teilenummer - ADN2817ACPZ |
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Ähnliche Beschreibung - ADN2817ACPZ |
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