Datenblatt-Suchmaschine für elektronische Bauteile |
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MCZ33903CP3EKR2 Datenblatt(PDF) 52 Page - Freescale Semiconductor, Inc |
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MCZ33903CP3EKR2 Datenblatt(HTML) 52 Page - Freescale Semiconductor, Inc |
52 / 106 page Analog Integrated Circuit Device Data 52 Freescale Semiconductor 33903/4/5 FAIL-SAFE OPERATION BEHAVIOR AT POWER UP AND POWER DOWN . Figure 30. Safe Operation Flow Chart Conditions to Set SAFE Pin Active Low Watchdog refresh issue: SAFE activated at 1st reset pulse or at the second consecutive reset pulse (selected by bit 4, INIT watchdog register). VDD low: VDD < RST-TH. SAFE pin is set low at the same time as the RST pin is set low. The RST pin is monitored to verify that reset is not clamped to a low level preventing the MCU to operate. If this is the case, the Safe mode is entered. watchdog failure VDD low: Rst s/c GND: - SAFE low 8 consecutive watchdog failure (5) State A: RDBG <6.0 k AND - SAFE low - Reset: 1.0 ms - VDD ON - Reset low INIT, b) ECU external signal State B1: RDBG =15k AND State B3: State B2: - SAFE low - Reset low - VDD OFF a) Evaluation of Bus idle timeout expired Normal, FLASH VDD <VDD_UVTH Rst <2.5 V, t >100 ms Device state: RESET NR bit 4, INIT watchdog = 1 (1) detection of 2nd consecutive watchdog failure SAFE low SAFE high SAFE low Reset: 1.0 ms pulse bit 4, INIT watchdog = 0 (1) Reset: 1.0 ms pulse Normal Request power up, or SPI at DBG pin during RESET SAFE pin release failure recovery, SAFE pin remains low SPI (3) AND Bus idle time out expired RESET Wake-up (2), VDD ON, SAFE pin remains low register content (SAFE high) Failure events 1) bit 4 of INIT Watchdog register 2) Wake-up event: CAN, LIN or I/O-1 high level (if I/O-1 Wake-up previously enabled) 3) SPI commands: 0xDD00 or 0xDD80 to release SAFE pin 4) Recovery: reset low condition released, VDD low condition released, correct SPI watchdog refresh 5) detection of 8 consecutive watchdog failures: no correct SPI watchdog refresh command occurred for duration of 8 x 256 ms. 6) Dynamic behavior: 1.0 ms reset pulse every 256 ms, due to no watchdog refresh SPI command, and device state transition Legend: RDBG = 33 k AND I/O-1 low RDBG = 47 k AND I/O-1 low - VDD ON (6) - SAFE low - VDD ON - Reset low periodic pulse State A: RDBG <6.0 k AND watchdog failure (VDD low or RST s/c GND) failure Resistor detected between RESET and NORMAL REQUEST mode, or INIT RESET and INIT modes. - bus idle time out - I/O-1 monitoring monitoring (7): 7) 8 second timer for bus idle timeout. I/O-1 high to low transition. SAFE Operation Flow Chart |
Ähnliche Teilenummer - MCZ33903CP3EKR2 |
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Ähnliche Beschreibung - MCZ33903CP3EKR2 |
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