Datenblatt-Suchmaschine für elektronische Bauteile |
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AD74111 Datenblatt(PDF) 4 Page - Analog Devices |
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AD74111 Datenblatt(HTML) 4 Page - Analog Devices |
4 / 20 page REV. 0 –4– AD74111 TIMING CHARACTERISTICS (AVDD = 2.5 V ± 5%, DVDD2 = 2.5 V ± 5%, DVDD1 = 3.3 V ± 10%, fMCLK = 12.288 MHz, fS = 48 kHz, TA = TMIN to TMAX, unless otherwise noted.) Parameter Min Max Unit Comments MASTER CLOCK AND RESET tMH MCLK High 25 ns tML MCLK Low 25 ns tRES RESET Low 10 ns tRS DIN Setup Time 5 MCLKS To RESET Rising Edge1 tRH DIN Setup Time 5 MCLKS To RESET Rising Edge1 SERIAL PORT tCH DCLK High 2 20 ns tCL DCLK Low 2 20 ns tFD DFS Delay 5 ns From DCLK Rising Edge 3 tFS DFS Setup Time 5 ns To DCLK Falling Edge tFH DFS Hold Time 15 ns From DCLK Falling Edge tDD DOUT Delay 30 ns From DCLK Rising Edge tDS DIN Setup Time 5 ns To DCLK Falling Edge tDH DIN Hold Time 15 ns From DCLK Falling Edge tDT DOUT Three-State 40 ns From DCLK Rising Edge 4 NOTES 1Determines Master/Slave mode operation. 2Applies in Slave mode only. 3Applies in Master mode only. 4Applies in Multiframe-Sync mode only. MCLK tMH RESET tML tRES tRS tRH DIN Figure 1. MCLK and RESET Timing MSB MSB–1 tFS DFS DCLK DIN DOUT MSB MSB–2 MSB–1 MSB–2 tFH tFD tDD tCH tCL tDS tDH Figure 2. Serial Port Timing 100 A IOL 100 A IOH CL 50pF TO OUTPUT PIN DVDD1 2 Figure 3. Load Circuit for Digital Output Timing Specifications |
Ähnliche Teilenummer - AD74111 |
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Ähnliche Beschreibung - AD74111 |
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