1 - Fs x 500 ns

RAMP

VCC

LM25574, LM25574-Q1

SNVS483G – JANUARY 2007 – REVISED APRIL 2013

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For duty cycles greater than 50%, peak current mode control circuits are subject to sub-harmonic oscillation.

Sub-harmonic oscillation is normally characterized by observing alternating wide and narrow pulses at the switch

node. Adding a fixed slope voltage ramp (slope compensation) to the current sense signal prevents this

oscillation. The 50µA of offset current provided from the emulated current source adds some fixed slope to the

ramp signal. In some high output voltage, high duty cycle applications, additional slope may be required. In these

compensation.

Maximum Duty Cycle / Input Drop-out Voltage

There is a forced off-time of 500ns implemented each cycle to guarantee sufficient time for the diode current to

be sampled. This forced off-time limits the maximum duty cycle of the buck switch. The maximum duty cycle will

vary with the operating frequency.

(3)

Where Fs is the oscillator frequency. Limiting the maximum duty cycle will raise the input dropout voltage. The

input dropout voltage is the lowest input voltage required to maintain regulation of the output voltage. An

approximation of the input dropout voltage is:

(4)

minimum input voltage necessary to maintain regulation.

Current Limit

The LM25574 contains a unique current monitoring scheme for control and over-current protection. When set

correctly, the emulated current sense signal provides a signal which is proportional to the buck switch current

with a scale factor of 2.0 V / A. The emulated ramp signal is applied to the current limit comparator. If the

emulated ramp signal exceeds 1.4V (0.7A) the present current cycle is terminated (cycle-by-cycle current

limiting). In applications with small output inductance and high input voltage the switch current may overshoot

due to the propagation delay of the current limit comparator. If an overshoot should occur, the diode current

sampling circuit will detect the excess inductor current during the off-time of the buck switch. If the sample & hold

DC level exceeds the 1.4V current limit threshold, the buck switch will be disabled and skip pulses until the diode

current sampling circuit detects the inductor current has decayed below the current limit threshold. This approach

prevents current runaway conditions due to propagation delays or inductor saturation since the inductor current is

forced to decay following any current overshoot.

12

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