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CAT1163LIWI-30-GT3 Datenblatt(PDF) 4 Page - ON Semiconductor

Teilenummer CAT1163LIWI-30-GT3
Bauteilbeschribung  Supervisory Circuits with Supervisory Circuits with
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Hersteller  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
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Table 6. AC CHARACTERISTICS
VCC = 2.7 V to 6.0 V unless otherwise specified. Output Load is TTL Gate and 100 pF.
Symbol
Parameter
VCC = 2.7 V − 6 V VCC = 4.5 V − 5.5 V
Units
Min
Max
Min
Max
FSCL
Clock Frequency
100
400
kHz
T1 (Note 1)
Noise Suppression Time Constant at SCL, SDA Inputs
200
200
ns
tAA
SCL Low to SDA Data Out and ACK Out
3.5
1
ms
tBUF (Note 1)
Time the Bus must be Free Before a New Transmission Can Start
4.7
1.2
ms
tHD; STA
Start Condition Hold Time
4
0.6
ms
tLOW
Clock Low Period
4.7
1.2
ms
tHIGH
Clock High Period
4
0.6
ms
tSU; STA
Start Condition Setup Time (for a Repeated Start Condition)
4.7
0.6
ms
tHD; DAT
Data in Hold Time
0
0
ns
tSU; DAT
Data in Setup Time
50
50
ns
tR (Note 1)
SDA and SCL Rise Time
1
0.3
ms
tF (Note 1)
SDA and SCL Fall Time
300
300
ns
tSU; STO
Stop Condition Setup Time
4
0.6
ms
tDH
Data Out Hold Time
100
100
ns
1. This parameter is tested initially and after a design or process change that affects the parameter.
Table 7. POWER−UP TIMING (Notes 1 and 2)
Symbol
Parameter
Min
Typ
Max
Units
tPUR
Power−up to Read Operation
1
ms
tPUW
Power−up to Write Operation
1
ms
2. tPUR and tPUW are the delays required from the time VCC is stable until the specific operation can be initiated.
Table 8. WRITE CYCLE LIMITS
Symbol
Parameter
Min
Typ
Max
Units
tWR
Write Cycle Time
10
ms
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write
cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
Table 9. RESET CIRCUIT CHARACTERISTICS
Symbol
Parameter
Min
Typ
Max
Units
tGLITCH
Glitch Reject Pulse Width
100
ns
VRT
Reset Threshold Hysteresis
15
mV
VOLRS
Reset Output Low Voltage (IOLRS = 1 mA)
0.4
V
VOHRS
Reset Output High Voltage
VCC − 0.75
V
VTH
Reset Threshold (VCC = 5 V), (CAT1163−45)
4.50
4.75
V
Reset Threshold (VCC = 5 V), (CAT1163−42)
4.25
4.50
Reset Threshold (VCC = 3.3 V), (CAT1163−30)
3.00
3.15
Reset Threshold (VCC = 3.3 V), (CAT1163−28)
2.85
3.00
Reset Threshold (VCC = 3 V), (CAT1163−25)
2.55
2.70
tPURST
Power−Up Reset Timeout
130
270
ms
tWP
Watchdog Period
1.6
s
tRPD
VTH to RESET Output Delay
5
ms
VRVALID
RESET Output Valid
1
V


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