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MC68EN360EM33L Datenblatt(PDF) 7 Page - Freescale Semiconductor, Inc |
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MC68EN360EM33L Datenblatt(HTML) 7 Page - Freescale Semiconductor, Inc |
7 / 14 page offers many more functions than even a 240-pin package would normally allow, resulting in more multifunctional pins than the MC68302. Software Compatibility Issues The following list summarizes the major software differences between the MC68302 and the QUICC: • Since the CPU32+ is a superset of the M68000 instruction set, all previously written code will run. However, if such code is accessing the MC68302 peripherals, it will require some modification. • The QUICC contains an 8-Kbyte block of memory as opposed to a 4-Kbyte block on the MC68302. The register addresses within that memory map are different. • The code used to initialize the system integration features of the MC68302 has to be modified to write the corresponding features on the QUICC SIM60. Code written for the MC68340 may be adapted in large part. • As much as possible, QUICC CPM features were made identical to those of the MC68302 CP. The most important benefit is that the code flow (if not the code itself) will port easily from the MC68302 to the QUICC. The nuances learned from the MC68302 will still be useful in the QUICC. • Although the registers used to initialize the QUICC CPM are new (for example, the SCM on the MC68302 is replaced with the GSMR and PSMR on the QUICC), most registers retain their original purpose such as the SCC event, SCC mask, SCC status, and command registers. The parameter RAM of the SCCs is very similar, and most parameter RAM register names and usage are retained. More importantly, the basic structure of a buffer descriptor (BD) on the QUICC is identical to that of the MC68302, except for a few new bit functions that were added. (In a few cases, a bit in a BD status word had to be shifted.) • When porting code from the MC68302 CP to the QUICC CPM, the software writer may find that the QUICC has new options to simplify what used to be a more code-intensive process. For specific examples, see the INIT TX AND RX PARAMETERS, GRACEFUL STOP TRANSMIT, and CLOSE BD commands. QUICC GLUELESS SYSTEM DESIGN A fundamental design goal of the QUICC was ease of interface to other system components. An example of this goal is a minimal QUICC design using EPROM and DRAM, shown in Figure 2. This system interfaces gluelessly to an EPROM and a DRAM SIMM module. It also offers parity support for the DRAM. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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