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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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ADSP-BF532SBBCZ400 Datenblatt(PDF) 5 Page - Analog Devices |
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ADSP-BF532SBBCZ400 Datenblatt(HTML) 5 Page - Analog Devices |
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5 / 64 page  ADSP-BF531/ADSP-BF532/ADSP-BF533 Rev. I | Page 5 of 64 | August 2013 The second on-chip memory block is the L1 data memory, con- sisting of one or two banks of up to 32K bytes. The memory banks are configurable, offering both cache and SRAM func- tionality. This memory block is accessed at full processor speed. The third memory block is a 4K byte scratchpad SRAM, which runs at the same speed as the L1 memories, but is only accessible as data SRAM and cannot be configured as cache memory. External (Off-Chip) Memory External memory is accessed via the external bus interface unit (EBIU). This 16-bit interface provides a glueless connection to a bank of synchronous DRAM (SDRAM) as well as up to four banks of asynchronous memory devices including flash, EPROM, ROM, SRAM, and memory mapped I/O devices. The PC133-compliant SDRAM controller can be programmed to interface to up to 128M bytes of SDRAM. The SDRAM con- troller allows one row to be open for each internal SDRAM bank, for up to four internal SDRAM banks, improving overall system performance. The asynchronous memory controller can be programmed to control up to four banks of devices with very flexible timing parameters for a wide variety of devices. Each bank occupies a 1M byte segment regardless of the size of the devices used, so that these banks are only contiguous if each is fully populated with 1M byte of memory. I/O Memory Space Blackfin processors do not define a separate I/O space. All resources are mapped through the flat 32-bit address space. On-chip I/O devices have their control registers mapped into memory mapped registers (MMRs) at addresses near the top of the 4G byte address space. These are separated into two smaller blocks, one containing the control MMRs for all core functions, and the other containing the registers needed for setup and con- trol of the on-chip peripherals outside of the core. The MMRs are accessible only in supervisor mode and appear as reserved space to on-chip peripherals. Booting The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors con- tain a small boot kernel, which configures the appropriate peripheral for booting. If the processors are configured to boot from boot ROM memory space, the processor starts executing from the on-chip boot ROM. For more information, see Boot- ing Modes on Page 14. Figure 2. Blackfin Processor Core SEQUENCER ALIGN DECODE LOOP BUFFER 16 16 8 88 8 40 40 A0 A1 BARREL SHIFTER DATAARITHMETIC UNIT CONTROL UNIT R7.H R6.H R5.H R4.H R3.H R2.H R1.H R0.H R7.L R6.L R5.L R4.L R3.L R2.L R1.L R0.L ASTAT 40 40 32 32 32 32 32 32 32 LD0 LD1 SD DAG0 DAG1 ADDRESS ARITHMETIC UNIT I3 I2 I1 I0 L3 L2 L1 L0 B3 B2 B1 B0 M3 M2 M1 M0 SP FP P5 P4 P3 P2 P1 P0 DA1 DA0 32 32 32 PREG RAB 32 |
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