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AD7843ARUZ Datenblatt(PDF) 5 Page - Analog Devices |
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AD7843ARUZ Datenblatt(HTML) 5 Page - Analog Devices |
5 / 21 page AD7843 Rev. B | Page 4 of 20 Parameter AD7843A1 Unit Test Conditions/Comments POWER REQUIREMENTS VCC (Specified Performance) 2.7/3.6 V min/max Functional from 2.2 V to 5.25 V ICC5 Digital I/Ps = 0 V or VCC Normal Mode (fSAMPLE = 125 kSPS) 380 µA max VCC = 3.6 V, 240 µA typ Normal Mode (fSAMPLE = 12.5 kSPS) 170 µA typ VCC = 2.7 V, fDCLK = 200 kHz Normal Mode (Static) 150 µA typ VCC = 3.6 V Shutdown Mode (Static) 1 µA max Power Dissipation5 Normal Mode (fSAMPLE = 125 kSPS) 1.368 mW max VCC = 3.6 V Shutdown 3.6 µW max VCC = 3.6 V 1 Temperature range as follows: A Version: −40°C to +85°C. 2 See the Terminology section. 3 Guaranteed by design. 4 Sample tested @ 25°C to ensure compliance. 5 See the Power vs. Throughput Rate section. TIMING SPECIFICATIONS TA = TMIN to TMAX, unless otherwise noted; VCC = 2.7 V to 3.6 V, VREF = 2.5 V. Table 2. Timing Specifications1 Parameter Limit at TMIN, TMAX Unit Description fDCLK2 10 kHz min 2 MHz max tACQ 1.5 µs min Acquisition time t1 10 ns min CS falling edge to First DCLK rising edge t2 60 ns max CS falling edge to BUSY three-state disabled t3 60 ns max CS falling edge to DOUT three-state disabled t4 200 ns min DCLK high pulse width t5 200 ns min DCLK low pulse width t6 60 ns max DCLK falling edge to BUSY rising edge t7 10 ns min Data setup time prior to DCLK rising edge t8 10 ns min Data valid to DCLK hold time t93 200 ns max Data access time after DCLK falling edge t10 0 ns min CS rising edge to DCLK ignored t11 200 ns max CS rising edge to BUSY high impedance t124 200 ns max CS rising edge to DOUT high impedance 1 Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VCC) and are timed from a voltage level of 1.6 V. 2 Mark/space ratio for the SCLK input is 40/60 to 60/40. 3 Measured with the load circuit in Figure 2 and defined as the time required for the output to cross 0.4 V or 2.0 V. 4 t12 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t12, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 200 µA 1.6V 200 µA IOL IOH TO OUTPUT PIN CL 50pF Figure 2. Load Circuit for Digital Output Timing Specifications |
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