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74AUP2G86GM Datenblatt(PDF) 10 Page - NXP Semiconductors

Teilenummer 74AUP2G86GM
Bauteilbeschribung  Low-power dual 2-input EXCLUSIVE-OR gate
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Hersteller  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
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74AUP2G86GM Datenblatt(HTML) 10 Page - NXP Semiconductors

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74AUP2G86
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 7 — 14 June 2012
10 of 21
NXP Semiconductors
74AUP2G86
Low-power dual 2-input EXCLUSIVE-OR gate
[1]
For measuring enable and disable times RL = 5 k.
For measuring propagation delays, set-up and hold times and pulse width RL = 1 M.
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 9.
Test circuit for measuring switching times
001aac521
DUT
RT
VI
VO
VEXT
VCC
RL
5 k
Ω
CL
G
Table 10.
Test data
Supply voltage
Load
VEXT
VCC
CL
RL[1]
tPLH, tPHL
tPZH, tPHZ
tPZL, tPLZ
0.8 V to 3.6 V
5 pF, 10 pF, 15 pF and 30 pF
5 k
 or 1 M
open
GND
2
 V
CC


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