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AM29LL800BT-150SC Datenblatt(PDF) 2 Page - Advanced Micro Devices

Teilenummer AM29LL800BT-150SC
Bauteilbeschribung  8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 2.2 Volt-only Boot Sector Flash Memory
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Hersteller  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

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Am29LL800B
ADV ANCE
I N FO RMAT I O N
GENERAL DESCRIPTION
The Am29LL800B is an 8 Mbit, 2.2 volt-only Flash
memory organized as 1,048,576 bytes or 524,288
words. The device is offered in 44-pin SO and 48-pin
TSOP packages. The word-wide data (x16) appears on
DQ15–DQ0; the byte-wide (x8) data appears on DQ7–
DQ0. This device requires only a single, 2.2 volt VCC
supply to perform read, program, and erase opera-
tions. A standard EPROM programmer can also be
used to program and erase the device.
This device is manufactured using AMD’s 0.35 µm pro-
cess technology, and offers all the features and bene-
fits of the Am29LV800, which was manufactured using
0. 5 µm proc es s t e c hnolo g y. In ad dit i on, the
Am29LL800B features unlock bypass programming
and in-system sector protection/unprotection.
The standard device offers access times of 150 and
200 ns, allowing high speed microprocessors to oper-
ate without wait states. To eliminate bus contention the
device has separate chip enable (CE#), write enable
(WE#) and output enable (OE#) controls.
The device requires only a single 2.2 volt power sup-
ply for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using stan-
dard microprocessor write timings. Register contents
serve as input to an internal state-machine that con-
trols the erase and programming circuitry. Write cycles
also internally latch addresses and data needed for the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase command
sequence. This initiates the Embedded Erase algo-
rithm—an internal algorithm that automatically prepro-
grams the array (if it is not already programmed) before
executing the erase operation. During erase, the device
automatically times the erase pulse widths and verifies
proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved in-system or via program-
ming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When ad-
dresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the standby
mode. Power consumption is greatly reduced in both
these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within
a sector simultaneously via Fowler-Nordheim tun-
neling. The data is programmed using hot electron in-
jection.


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