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74LVC8T245PW Datenblatt(PDF) 2 Page - NXP Semiconductors |
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74LVC8T245PW Datenblatt(HTML) 2 Page - NXP Semiconductors |
2 / 28 page 74LVC_LVCH8T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 12 December 2011 2 of 28 NXP Semiconductors 74LVC8T245; 74LVCH8T245 8-bit dual supply translating transceiver; 3-state 60 Mbps (translate to 1.5 V) Suspend mode Latch-up performance exceeds 100 mA per JESD 78B Class II 24 mA output drive (V CC =3.0 V) Inputs accept voltages up to 5.5 V Low power consumption: 30 A maximum I CC IOFF circuitry provides partial Power-down mode operation Multiple package options Specified from 40 Cto+85 C and 40 Cto+125 C 3. Ordering information 4. Functional diagram Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC8T245PW 40 C to +125 C TSSOP24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1 74LVCH8T245PW 74LVC8T245BQ 40 C to +125 C DHVQFN24 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 5.5 0.85 mm SOT815-1 74LVCH8T245BQ Fig 1. Logic symbol 001aai472 OE DIR VCC(A) VCC(B) 22 2 3 A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 45678910 21 20 19 18 17 16 15 14 |
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