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AM29LV640DL121RWHI Datenblatt(PDF) 3 Page - Advanced Micro Devices

Teilenummer AM29LV640DL121RWHI
Bauteilbeschribung  64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory with VersatileI Control
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Hersteller  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

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Am29LV640D/Am29LV641D
September 20, 2002
GENERAL DESCRIPTION
The Am29LV640DU/Am29LV641DU is a 64 Mbit, 3.0
Volt (3.0 V to 3.6 V) single power supply flash memory
devices organized as 4,194,304 words. Data appears
on DQ0-DQ15. The device is designed to be pro-
grammed in-system with the standard system 3.0 volt
V
CC supply. A 12.0 volt VPP is not required for program
or erase operations. The device can also be pro-
grammed in standard EPROM programmers.
Access times of 90 and 120 ns are available for appli-
cations where V
IO ≥ VCC. Access times of 100 and 120
ns are available for applications where V
IO < VCC. The
device is offered in 48-pin TSOP, 56-pin SSOP, 63-ball
Fine-Pitch BGA and 64-ball Fortified BGA packages.
To eliminate bus contention each device has separate
chip enable (CE#), write enable (WE#) and output en-
able (OE#) controls.
Each device requires only a single 3.0 Volt power
supply (3.0 V to 3.6 V) for both read and write func-
tions. Internally generated and regulated voltages are
provided for the program and erase operations.
The device is entirely command set compatible with
the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timing. Register con-
tents serve as inputs to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data
needed for the programming and erase operations.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically
p re pro grams the arra y (if it is n ot a lre ad y pro-
grammed) before executing the erase operation. Dur-
ing erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The VersatileIO™ (V
IO) control allows the host system
to set the voltage levels that the device generates and
tolerates on CE# and DQ I/Os to the same voltage
level that is asserted on V
IO. VIO is available in two
configurations (1.8–2.9 V and 3.0–5.0 V) for operation
in various system environments.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, by reading the DQ7 (Data# Polling), or DQ6 (tog-
gle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
The sector erase architecture allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
V
CC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of sectors of memory.
This can be achieved in-system or via programming
equipment.
The Erase Suspend/Erase Resume feature enables
the user to put erase on hold for any period of time to
read data from, or program data to, any sector that is
not selected for erasure. True background erase can
thus be achieved.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to
the system reset circuitry. A system reset would thus
also reset the device, enabling the system micropro-
cessor to read boot-up firmware from the Flash mem-
ory device.
The device offers a standby mode as a power-saving
feature. Once the system places the device into the
standby mode power consumption is greatly reduced.
The SecSi (Secured Silicon) Sector provides an
minimum 128-word area for code or data that can be
permanently protected. Once this sector is protected,
no further programming or erasing within the sector
can occur.
The Write Protect (WP#) feature protects the first or
last sector by asserting a logic low on the WP# pin.
The protected sector will still be protected even during
accelerated programming.
The accelerated program (ACC) feature allows the
system to program the device at a much faster rate.
When ACC is pulled high to V
HH, the device enters the
Unlock Bypass mode, enabling the user to reduce the
time needed to do the program operation. This feature
is intended to increase factory throughput during sys-
tem production, but may also be used in the field if de-
sired.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunnelling.
The data is programmed using hot electron injection.


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