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74LVC2G00GF Datenblatt(PDF) 7 Page - NXP Semiconductors |
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74LVC2G00GF Datenblatt(HTML) 7 Page - NXP Semiconductors |
7 / 20 page 74LVC2G00 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 12 — 8 April 2013 7 of 20 NXP Semiconductors 74LVC2G00 Dual 2-input NAND gate 11. Dynamic characteristics [1] Typical values are measured at nominal VCC and at Tamb = 25 C. [2] tpd is the same as tPLH and tPHL [3] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (C L VCC 2 f o) = sum of outputs. 12. Waveforms Table 8. Dynamic characteristics Voltages are referenced to GND (ground 0 V); for test circuit see Figure 9. Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ[1] Max Min Max tpd propagation delay nA, nB to nY; see Figure 8 [2] VCC = 1.65 V to 1.95 V 1.2 3.5 8.6 1.2 10.8 ns VCC = 2.3 V to 2.7 V 0.7 2.3 4.8 0.7 6.0 ns VCC = 2.7 V 0.7 3.0 5.6 0.7 7.0 ns VCC = 3.0 V to 3.6 V 0.7 2.2 4.3 0.7 5.4 ns VCC = 4.5 V to 5.5 V 0.5 1.8 3.3 0.5 4.2 ns CPD power dissipation capacitance per gate; VI = GND to VCC [3] -14 - - - pF Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. Fig 8. Input (nA, nB) to output (nY) propagation delays 001aae972 nA, nB input nY output tPLH tPHL GND VI VM VM VOH VOL |
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