AD7812YN datasheet(3/19 Pages) AD

Teilenummer	AD7812YN

Bauteilbeschribung	2.7 V to 5.5 V, 350 kSPS, 10-Bit 4-/8-Channel Sampling ADCs

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REV. B

AD7811/AD7812

Parameter

Y Version

Unit

Test Conditions/Comments

POWER SUPPLY

VDD

2.7

V min

For Specified Performance

5.5

V max

IDD

Digital Inputs = 0 V or VDD

Normal Operation

3.5

mA max

Power-Down

Full Power-Down

1

µA max

Partial Power-Down (Internal Ref)

350

µA max

See Power-Up Times Section

Power Dissipation

VDD = 3 V

Normal Operation

10.5

mW max

Auto Full Power-Down

See Power vs. Throughput Section

Throughput 1 kSPS

31.5

µW max

Throughput 10 kSPS

315

µW max

Throughput 100 kSPS

3.15

mW max

Partial Power-Down (Internal Ref)

1.05

mW max

Full Power-Down

3

µW max

NOTES

1See Terminology.

2Sample tested during initial release and after any redesign or process change that may affect this parameter.

Specifications subject to change without notice.

TIMING CHARACTERISTICS1, 2

Parameter

Y Version

Unit

Conditions/Comments

t

POWER-UP

1.5

µs (max)

Power-Up Time of AD7811/AD7812 after Rising Edge of

CONVST

t

1

2.3

µs (max)

Conversion Time

t

2

20

ns (min)

CONVST Pulsewidth

t

3

25

ns (min)

SCLK High Pulsewidth

t

4

25

ns (min)

SCLK Low Pulsewidth

t

5

3

5

ns (min)

RFS Rising Edge to SCLK Rising Edge Setup Time

t

6

3

5

ns (min)

TFS Falling Edge to SCLK Falling Edge Setup Time

t

7

3

10

ns (max)

SCLK Rising Edge to Data Out Valid

t

8

10

ns (min)

DIN Data Valid to SCLK Falling Edge Setup Time

t

9

5

ns (min)

DIN Data Valid after SCLK Falling Edge Hold Time

t

10

3, 4

20

ns (max)

SCLK Rising Edge to DOUT High Impedance

t

11

100

ns (min)

DOUT High Impedance to

CONVST Falling Edge

NOTES

1Sample tested to ensure compliance.

2See Figures 16, 17 and 18.

3These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for V

DD = 5 V

± 10% and

0.4 V or 2 V for VDD = 3 V

± 10%.

4Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back

to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 11, quoted in the Timing Characteristics is the true bus relinquish

time of the part and as such is independent of external bus loading capacitances.

Specifications subject to change without notice.

(VDD = 2.7 V to 5.5 V, VREF = VDD [EXT] unless otherwise noted)

2.1V

200 A

CL

50pF

IOH

TO

OUTPUT

IOL

200 A

Figure 1. Load Circuit for Digital Output Timing Specifications

Ähnliche Beschreibung - AD7812YN

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Analog Devices	AD7811YRUZ	211Kb / 19P	2.7 V to 5.5 V, 350 kSPS, 10-Bit 4-/8-Channel Sampling ADCs REV. B
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	AD7813	194Kb / 11P	2.7 V to 5.5 V, 400 kSPS 8-/10-Bit Sampling ADC REV. C
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