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AD8314-EVAL Datenblatt(PDF) 10 Page - Analog Devices |
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AD8314-EVAL Datenblatt(HTML) 10 Page - Analog Devices |
10 / 20 page AD8314 Rev. B | Page 10 of 20 THEORY OF OPERATION The AD8314 is a logarithmic amplifier (log amp) similar in design to the AD8313; further details about the structure and function can be found in the AD8313 data sheet and other log amps produced by ADI. Figure 28 shows the main features of the AD8314 in block schematic form. The AD8314 combines two key functions needed for the measurement of signal level over a moderately wide dynamic range. First, it provides the amplification needed to respond to small signals, in a chain of four amplifier/limiter cells, each having a small signal gain of 10 dB and a bandwidth of approximately 3.5 GHz. At the output of each of these amplifier stages is a full-wave rectifier, essentially a square-law detector cell, that converts the RF signal voltages to a fluctuating current having an average value that increases with signal level. A further passive detector stage is added prior to the first stage. Therefore, there are five detectors, each separated by 10 dB, spanning some 50 dB of dynamic range. The overall accuracy at the extremes of this total range, viewed as the deviation from an ideal logarithmic response, that is, the law-conformance error, can be judged by reference to Figure 7, which shows that errors across the central 40 dB are moderate. Figure 5, Figure 6, Figure 8 through Figure 11, Figure 13, and Figure 14 show how the conformance to an ideal logarithmic function varies with supply voltage, temperature, and frequency. The output of these detector cells is in the form of a differential current, making their summation a simple matter. It can easily be shown that such summation closely approximates a logarithmic function. This result is then converted to a voltage, at Pin V_UP, through a high-gain stage. In measurement modes, this output is connected back to a voltage-to-current (V-I) stage, in such a manner that V_UP is a logarithmic measure of the RF input voltage, with a slope and intercept controlled by the design. For a fixed termination resistance at the input of the AD8314, a given voltage corresponds to a certain power level. However, in using this part, it must be understood that log amps do not fundamentally respond to power. It is for this reason the dBV is used (decibels above 1 V rms) rather than the commonly used metric of dBm. While the dBV scaling is fixed, independent of termination impedance, the corresponding power level is not. For example, 224 mV rms is always −13 dBV (with one further condition of an assumed sinusoidal waveform; see the Applications section for more information on the effect of waveform on logarithmic intercept), and it corresponds to a power of 0 dBm when the net impedance at the input is 50 Ω. When this impedance is altered to 200 Ω, the same voltage clearly represents a power level that is four times smaller (P = V2/R), that is, −6 dBm. Note that dBV can be converted to dBm for the special case of a 50 Ω system by simply adding 13 dB (0 dBV is equivalent to +13 dBm). Therefore, the external termination added prior to the AD8314 determines the effective power scaling. This often takes the form of a simple resistor (52.3 Ω provides a net 50 Ω input), but more elaborate matching networks can be used. This impedance determines the logarithmic intercept, the input power for which the output would cross the baseline (V_UP = zero) if the function were continuous for all values of input. Because this is never the case for a practical log amp, the intercept refers to the value obtained by the minimum-error straight-line fit to the actual graph of V_UP vs. PIN (more generally, VIN). Again, keep in mind that the quoted values assume a sinusoidal (CW) signal. Where there is complex modulation, as in CDMA, the calibration of the power response needs to be adjusted accordingly. Where a true power (waveform- independent) response is needed, the use of an rms-responding detector, such as the AD8361, should be considered. 10dB OFFSET COMPENSATION V-I I-V RFIN COMM (PADDLE) VPOS X2 ENBL V_DN V_UP VSET FLTR AD8314 10dB 10dB 10dB BAND GAP REFERENCE DET DET + – – + DET DET DET Figure 28. Block Schematic |
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