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DAC5687IPZPR Datenblatt(PDF) 10 Page - Texas Instruments |
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DAC5687IPZPR Datenblatt(HTML) 10 Page - Texas Instruments |
10 / 79 page www.ti.com CLK 2 1 0.5 2f - DAC5687 SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 ELECTRICAL CHARACTERISTICS (DIGITAL SPECIFICATIONS) (continued) over recommended operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V, DVDD = 1.8 V, IOUTFS = 19.2 mA (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PLL At 600-kHz offset, measured at DAC output, 25-MHz, 0-dBFS tone, fDATA = 125 MSPS, 133 4 × interpolation, pll_freq = 1, pll_kv = 0 Phase noise dBc/Hz At 6-MHz offset, measured at DAC output, 25 MHz 0-dBFS tone, 125 MSPS, 148.5 4 × interpolation, pll_freq = 1, pll_kv = 0 pll_freq = 0, pll_kv = 1 370 pll_freq = 0, pll_kv = 0 480 VCO maximum frequency MHz pll_freq = 1, pll_kv = 1 495 pll_freq = 1, pll_kv = 0 520 pll_freq = 0, pll_kv = 1 225 pll_freq = 0, pll_kv = 0 200 VCO minimum frequency MHz pll_freq = 1, pll_kv = 1 480 pll_freq = 1, pll_kv = 0 480 NCO and QMC BLOCKS QMC clock rate 320 MHz NCO clock rate 320 MHz SERIAL PORT TIMING ts(SDENB) Setup time, SDENB to rising edge of SCLK 20 ns Setup time, SDIO valid to rising edge of ts(SDIO) 10 ns SCLK Hold time, SDIO valid to rising edge of th(SDIO) 5 ns SCLK tSCLK Period of SCLK 100 ns tSCLKH High time of SCLK 40 ns tSCLK Low time of SCLK 40 ns Data output delay after falling edge of td(Data) 10 ns SCLK CLOCK INPUT (CLK1/CLK1C, CLK2/CLK2C) Duty cycle 40% 60% Differential voltage 0.4 1 V TIMING PARALLEL DATA INPUT: CLK1 LATCHING MODES (PLL Mode – See Figure 45, Dual Clock Mode FIFO Disabled – See Figure 47, Dual Clock Mode With FIFO Enabled – See Figure 48) Setup time, DATA valid to rising edge of ts(DATA) 0.5 ns CLK1 Hold time, DATA valid after rising edge of th(DATA) 1.5 ns CLK1 Maximum offset between CLK1 and CLK2 t_align rising edges – dual clock mode with FIFO ns disabled Timing Parallel Data Input (External Clock Mode, Latch on PLLLOCK Rising Edge, CLK2 Clock Input, See Figure 43 ) Setup time, DATA valid to rising edge of ts(DATA) 72- Ω load on PLLLOCK 0.5 ns PLLLOCK Hold time, DATA valid after rising edge of th(DATA) 72- Ω load on PLLLOCK 1.5 ns PLLLOCK Delay from CLK2 rising edge to PLLLOCK 72- Ω load on PLLLOCK. Note that PLLLOCK tdelay(Plllock) 4.5 ns rising edge delay increases with a lower-impedance load. Timing Parallel Data Input (External Clock Mode, Latch on PLLLOCK Falling Edge, CLK2 Clock Input, See Figure 44) Setup time, DATA valid to falling edge of ts(DATA) High-impedance load on PLLLOCK 0.5 ns PLLLOCK Hold time, DATA valid after falling edge of th(DATA) High-impedance load on PLLLOCK 1.5 ns PLLLOCK High-impedance load on PLLLOCK. Note that Delay from CLK2 rising edge to PLLLOCK tdelay(Plllock) PLLLOCK delay increases with a 4.5 ns rising edge lower-impedance load. 10 Submit Documentation Feedback Copyright © 2005–2006, Texas Instruments Incorporated Product Folder Link(s): DAC5687 |
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