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74LVC00APW Datenblatt(PDF) 11 Page - NXP Semiconductors |
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74LVC00APW Datenblatt(HTML) 11 Page - NXP Semiconductors |
11 / 14 page 74LVC00A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 7 — 25 April 2012 11 of 14 NXP Semiconductors 74LVC00A Quad 2-input NAND gate 13. Abbreviations 14. Revision history Table 9. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC00A v.7 20120425 Product data sheet - 74LVC00A v.6 Modifications: • Table 2: Errata in pin description corrected. 74LVC00A v.6 20120106 Product data sheet - 74LVC00A v.5 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Table 4, Table 5, Table 6, Table 7 and Table 8: values added for lower voltage ranges. 74LVC00A v.5 20030904 Product specification - 74LVC00A v.4 74LVC00A v.4 20030507 Product specification - 74LVC00A v.3 74LVC00A v.3 20020305 Product specification - 74LVC00A v.2 74LVC00A v.2 19980428 Product specification - 74LVC00A v.1 74LVC00A v.1 19970811 Product specification - - |
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