7

®

DAC2814

MODE

CLR

CLK

CS

LATCH A

LATCH B

FUNCTION

X1

↓

0

X

X

Data Clocked In

X

1

X

1

X

X

No Data Transfer

X

1

X

0

0

1

DAC A Register Updated

X

1

X

0

1

0

DAC B Register Updated

X

1

X

0

0

0

DAC A and DAC B Updated Together

0

0

X

X

X

X

All Registers Cleared

1

0

X

X

X

X

NOTE: X = Don’t care

↓ = Falling edge triggered.

t1

t3

t2

t8

t7

t4

t6

t5

CLK

Data

CS

LATCH A

LATCH B

CLR

0V

5V

0V

5V

5V

5V

NOTES: (1) All input signal rise and fall times are measured from 10% to 90% of +5V • t = t = 5ns.

(2) Timing measurement reference level is V

+ V .

R

F

IH

IL

2

TIMING CHARACTERISTICS

PARAMETER

MINIMUM

15ns

15ns

15ns

Latch, Data Setup Time

40ns

Latch, Data Hold Time

40ns

40ns

40ns

15ns

or LATCH B

INTERFACE LOGIC TRUTH TABLE

10k

Ω

10k

Ω

20k

Ω

20k

Ω

20k

Ω

20k

Ω

6

18

17

+V

L

BPO B

V

B

OUT

DAC B

19

14

BPO A

V

A

OUT

DAC A

12 Inv Out

Control

Logic

12-Bit

Latch

Register

12-Bit

Shift

Register

12-Bit

Latch

Register

12-Bit

Shift

Register

Bits 0-11

0-11

Bits 0-11

0-11

5

15

16

1

7

10

8

4

MODE

CLR

LATCH B

LATCH A 22

+V

S

–V

S

DGND +V

Out

REF

Inv In

AGND

Data Out

23

Data In

11

V

In

REF

Bit 11

Bit 11

+10V

Voltage

Reference

CLK

2

21

CS 24

3

A

3

A

2

A

1