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DAC712 Datenblatt(PDF) 4 Page - Burr-Brown (TI) |
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DAC712 Datenblatt(HTML) 4 Page - Burr-Brown (TI) |
4 / 12 page 4 ® DAC712 ABSOLUTE MAXIMUM RATINGS +VCC to COMMON ...................................................................... 0V, +17V –VCC to COMMON ...................................................................... 0V, –17V +VCC to –VCC ........................................................................................ 34V Digital Inputs to COMMON .......................................... –1V to +VCC –0.7V External Voltage Applied to BPO and Range Resistors ..................... ±V CC VREF OUT ...................................................... Indefinite Short to COMMON VOUT ............................................................ Indefinite Short to COMMON Power Dissipation .......................................................................... 750mW Storage Temperature ...................................................... –60 °C to +150°C Lead Temperature (soldering, 10s) ................................................ +300 °C NOTE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. PACKAGE DRAWING PRODUCT PACKAGE NUMBER(1) DAC712P Plastic DIP 246 DAC712U Plastic SOIC 217 DAC712PB Plastic DIP 246 DAC712UB Plastic SOIC 217 DAC712PK Plastic DIP 246 DAC712UK Plastic SOIC 217 DAC712PL Plastic DIP 246 DAC712UL Plastic SOIC 217 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. PACKAGE INFORMATION TIMING DIAGRAM TIMING SPECIFICATIONS TA = –40°C to +85°C, +VCC = +12V or +15V, –VCC = –12V or –15V. SYMBOL PARAMETER MIN MAX UNITS tDW Data Valid to End of WR 50 ns tAW A0, A1 Valid to End of WR 50 ns tAH A0, A1 Hold after End of WR 10 ns tDH Data Hold after end of WR 10 ns tWP(1) Write Pulse Width 50 ns tCP CLEAR Pulse Width 200 ns NOTES: (1) For single-buffered operation, tWP is 80ns min. Refer to page 10. WR A 0, A1 D0-D15 t DH t AW t WP t DW t AH A0 A1 WR CLR DESCRIPTION 01 1 → 0 → 1 1 Load Input Latch 10 1 → 0 → 1 1 Load D/A Latch 11 1 → 0 → 1 1 No Change 0 0 0 1 Latches Transparent X X 1 1 No Change X X X 0 Reset D/A Latch TRUTH TABLE ELECTROSTATIC DISCHARGE SENSITIVITY Electrostatic discharge can cause damage ranging from per- formance degradation to complete device failure. Burr-Brown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published speci- fications. ORDERING INFORMATION LINEARITY DIFFERENTIAL TEMPERATURE ERROR MAX LINEARITY ERROR PRODUCT RANGE at +25 °C MAX at +25 °C DAC712P –40 °C to +85°C ±4LSB ±4LSB DAC712U –40 °C to +85°C ±4LSB ±4LSB DAC712PB –40 °C to +85°C ±2LSB ±2LSB DAC712UB –40 °C to +85°C ±2LSB ±2LSB DAC712PK 0 °C to +70°C ±2LSB ±2LSB DAC712UK 0 °C to +70°C ±2LSB ±2LSB DAC712PL 0 °C to +70°C ±2LSB ±1LSB DAC712UL 0 °C to +70°C ±2LSB ±1LSB |
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Ähnliche Beschreibung - DAC712 |
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