Datenblatt-Suchmaschine für elektronische Bauteile |
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DAC725KP Datenblatt(PDF) 5 Page - Burr-Brown (TI) |
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DAC725KP Datenblatt(HTML) 5 Page - Burr-Brown (TI) |
5 / 7 page 5 ® DAC725 Gain Adjustment To adjust the gain of the DAC725, set the DAC to 7FFF H for both DACs. Adjust the gain of each DAC to obtain the full scale voltage of +9.99969V as shown in Table II. FIGURE 2. Power Supply Rejection Versus Power Supply Ripple Frequency. OPERATING INSTRUCTIONS POWER SUPPLY CONNECTIONS For optimum performance and noise rejection, power supply decoupling capacitors should be added as shown in the Connection Diagram. 1 µF to 10µF tantalum capacitors should be located close to the D/A converter. EXTERNAL ZERO AND GAIN ADJUSTMENT Zero and gain may be trimmed by installing external zero and gain potentiometers. Connect these potentiometers as shown in the Connection Diagram and adjust as described below. TCR of the potentiometers should be 100ppm/ °C or less. The 3.9M Ω and 270kΩ resistors (±20% carbon or better) should be located close to the D/A converter to prevent noise pickup. If it is not convenient to use these high-value resistors, an equivalent “T” network, as shown in Figure 3, may be substituted in place of the 3.9M Ω resistor. A 0.001 µF to 0.01µF low-leakage film capacitor should be connected from Gain Adjust to Analog Common to prevent noise pickup. Refer to Figure 4 for relationship of Offset and Gain adjustments. FIGURE 3. Equivalent Resistances. 180k Ω 180k Ω 3.9M Ω 10k Ω Zero Adjustment By loading the code 0000H, the DAC will force 0V. Offset is adjusted by using the circuit of Figure 5. An alternate method would be to use the CLR control to set the DAC to 0V. Zero calibration should be made before gain calibration. BIPOLAR OUTPUT, ±10V DIGITAL INPUT CODE 16 Bits 15 Bits 14 Bits UNITS One LSB 305 610 1224 µV 7FFFH +9.99969 +9.99939 +9.99878 V 8000H –10 –10 –10 V TABLE II. Digital Input Codes. INTERFACE LOGIC AND TIMING The control logic functions are chip select (CS A or CSB), write (WRA or WRB), latch enable (A0, A1, A2), and clear (CLR). These pins provide the control functions for the micro- processor interface. There is a write and a chip select for both DAC A and for DACB channels. This allows the 8-bit data word to be latched from the data bus to the input latch or from the input latch to the DAC latch, of DAC A, DACB, or both. A0 A 1 A2 WR (A) CS (A) DESCRIPTION 1 1 0 0 0 DAC latch enabled, Channel A 1 0 1 0 0 Input latch high byte enabled, Channel A 1 0 0 0 0 High byte flows through to DAC, Channel A 0 1 1 0 0 Low byte latched from data bus, Channel A 0 1 0 0 0 Low byte flows through to DAC, Channel A 0 0 1 1 1 Serial input mode for byte latches X X X 1 0 No data is latched X X X 0 1 No data is latched “1” or “0” indicates TTL Logic Level Channel A shown. TABLE III. Truth Table of Data Transfers. FIGURE 4. Relationship of Zero and Gain Adjustments for the DAC725. Range of Gain Adjust Offset Adjust Translates the Line Range and Offset Adjust 1LSB + Full Scale Input = 8000 H Input = 7FFF H Input = 0000 H – Full Scale Digital Input Gain Adjust Rotates the Line 1 Power Supply Ripple Frequency (Hz) 10 100 1k 10k 100k 0.03 0.025 0.02 0.015 0.01 0.005 0 –15V Supply +15V Supply +5V Supply |
Ähnliche Teilenummer - DAC725KP |
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Ähnliche Beschreibung - DAC725KP |
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