Datenblatt-Suchmaschine für elektronische Bauteile |
|
AD5686 Datenblatt(PDF) 10 Page - Analog Devices |
|
AD5686 Datenblatt(HTML) 10 Page - Analog Devices |
10 / 28 page AD5686/AD5684 Data Sheet Rev. A | Page 10 of 28 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 6. 16-Lead LFCSP Pin Configuration Figure 7. 16-Lead TSSOP Pin Configuration Table 7. Pin Function Descriptions Pin No. Mnemonic Description LFCSP TSSOP 1 3 VOUTA Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. 2 4 GND Ground Reference Point for All Circuitry on the Part. 3 5 VDD Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. 4 6 VOUTC Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. 5 7 VOUTD Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. 6 8 SDO Serial Data Output. Can be used to daisy-chain a number of AD5686/AD5684 devices together or can be used for readback. The serial data is transferred on the rising edge of SCLK and is valid on the falling edge of the clock. 7 9 LDAC LDAC can be operated in two modes, asynchronously and synchronously. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs to be simultaneously updated. This pin can also be tied permanently low. 8 10 GAIN Span Set Pin. When this pin is tied to GND, all four DAC outputs have a span from 0 V to VREF. When this pin is tied to VLOGIC, all four DAC outputs have a span from 0 V to 2 × VREF. 9 11 VLOGIC Digital Power Supply. Voltage ranges from 1.8 V to 5.5 V. 10 12 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz. 11 13 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, data is transferred in on the falling edges of the next 24 clocks. 12 14 SDIN Serial Data Input. These devices have a 24-bit input shift register. Data is clocked into the register on the falling edge of the serial clock input. 13 15 RESET Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC pulses are ignored. When RESET is activated, the input register and the DAC register are updated with zero scale or midscale, depending on the state of the RSTSEL pin. 14 16 RSTSEL Power-On Reset Pin. Tying this pin to GND powers up all four DACs to zero scale. Tying this pin to VLOGIC powers up all four DACs to midscale. 15 1 VREF Reference Input Voltage. 16 2 VOUTB Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. 17 N/A EPAD Exposed Pad. The exposed pad must be tied to GND. 12 11 10 1 3 4 SDIN SYNC SCLK 9 VLOGIC VOUTA VDD 2 GND VOUTC AD5686/AD5684 NOTES 1. THE EXPOSED PAD MUST BE TIED TO GND. TOP VIEW (Not to Scale) 1 2 3 4 5 6 7 8 VOUTB VOUTA GND VOUTD VOUTC VDD VREF SDO 16 15 14 13 12 11 10 9 RESET SDIN SYNC GAIN LDAC VLOGIC SCLK RSTSEL TOP VIEW (Not to Scale) AD5686/ AD5684 |
Ähnliche Teilenummer - AD5686 |
|
Ähnliche Beschreibung - AD5686 |
|
|
Link URL |
Privatsphäre und Datenschutz |
ALLDATASHEETDE.COM |
War ALLDATASHEET hilfreich? [ DONATE ] |
Über Alldatasheet | Werbung | Kontakt | Privatsphäre und Datenschutz | Linktausch | Hersteller All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |