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CAT22C10JI-30TE13 Datenblatt(PDF) 6 Page - Catalyst Semiconductor |
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CAT22C10JI-30TE13 Datenblatt(HTML) 6 Page - Catalyst Semiconductor |
6 / 10 page CAT22C10 6 Doc. No. 25018-0A 2/98 N-1 DEVICE OPERATION The configuration of the CAT22C10 allows a common address bus to be directly connected to the address inputs. Additionally, the Input/Output (I/O) pins can be directly connected to a common I/O bus if the bus has less than 1 TTL load and 100pF capacitance. If not, the I/O path should be buffered. When the chip select ( CS) pin goes low, the device is activated. When CS is forced high, the device goes into the standby mode and consumes very little current. With the nonvolatile functions inhibited, the device operates like a Static RAM. The Write Enable ( WE) pin selects a write operation when WE is low and a read operation when WE is high. In either of these modes, an array byte (4 bits) can be addressed uniquely by using the address lines (A0–A5), and that byte will be read or written to through the Input/Output pins (I/O0–I/O3). The nonvolatile functions are inhibited by holding the STORE input and the RECALL input high. When the RECALL input is taken low, it initiates a recall operation which transfers the contents of the entire E2PROM array into the Static RAM. When the STORE input is taken low, it initiates a store operation which transfers the entire Static RAM array contents into the E2PROM array. Standby Mode The chip select ( CS) input controls all of the functions of the CAT22C10. When a high level is supplied to the CS pin, the device goes into the standby mode where the outputs are put into a high impendance state and the power consumption is drastically reduced. With ISB less than 100 µA in standby mode, the designer has the flexibility to use this part in battery operated systems. Read When the chip is enabled ( CS = low), the nonvolatile functions are inhibited ( STORE = high and RECALL = high). With the Write Enable ( WE) pin held high, the data in the Static RAM array may be accessed by selecting an address with input pins A0–A5. This will occur when the outputs are connected to a bus which is loaded by no more than 100pF and 1 TTL gate. If the loading is greater than this, some additional buffering circuitry is recom- mended. Figure 1. Read Cycle Timing 5153 FHD F06 ADDRESS CS DATA I/O tRC tCO tAA tLZ tOH tHZ HIGH-Z DATA VALID |
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Ähnliche Beschreibung - CAT22C10JI-30TE13 |
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