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CAT25C05 Datenblatt(PDF) 7 Page - Catalyst Semiconductor

Teilenummer CAT25C05
Bauteilbeschribung  2K/4K/8K/16K/32K SPI Serial CMOS E2PROM
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Hersteller  CATALYST [Catalyst Semiconductor]
Direct Link  http://www.catalyst-semiconductor.com
Logo CATALYST - Catalyst Semiconductor

CAT25C05 Datenblatt(HTML) 7 Page - Catalyst Semiconductor

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7
CAT25C03/05/09/17/33
Doc. No. 25068-00 2/98
Advanced
Figure 4. Read Instruction Timing
Byte Write
Once the device is in a Write Enable state, the user may
proceed with a write sequence by setting the
CS low,
issuing a write instruction via the SI line, followed by the
16-bit address for 25C09/17/33. (only 10-bit addresses
are used for 25C09, 11-bit addresses are used for
25C17, and 12-bit addresses are used for 25C33. The
rest of the bits are don't care bits) and 8-bit address for
25C03/05 (for the 25C05, bit 3 of the read data instruc-
tion contains address A8). Programming will start after
the
CS is brought high. The low to high transition of the
CS pin must occur during the SCK low time, immediately
after clocking the least significant bit of the data. Figure
6 illustrates byte write sequence.
SK
SI
CS
SO
RESET
0000001
1
BYTE ADDRESS*
0123456789
10
20
21
22
23
24
25
26
27
28
29
30
7
6
5
4
3
2
1
0
*Please check the instruction set table for address
WRITE Sequence
The CAT25C03/05/09/17/33 powers up in a Write Dis-
able state. Prior to any write instructions, the WREN
instruction must be sent to CAT25C03/05/09/17/33.
The device goes into Write enable state by pulling the
CS low and then clocking the WREN instruction into
CAT25C03/05/09/17/33. The
CS must be brought high
after the WREN instruction to enable writes to the
device. If the write operation is initiated immediately after
the WREN instruction without
CS being brought high,
the data will not be written to the array because the write
enable latch will not have been properly set. Also, for a
successful write operation the address of the memory
location(s) to be programmed must be outside the
protected address field.
Figure 5. RDSR Timing
25C03 F09
0
1
2
345
67
8
10
911
12
13
14
CS
SCK
SI
SO
HIGH IMPEDANCE
MSB
DATA OUT
0
21
76
5
4
3


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