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74HC4053BQ-Q100 Datenblatt(PDF) 4 Page - NXP Semiconductors |
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74HC4053BQ-Q100 Datenblatt(HTML) 4 Page - NXP Semiconductors |
4 / 30 page 74HC_HCT4053_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 2 — 22 November 2012 4 of 30 NXP Semiconductors 74HC4053-Q100; 74HCT4053-Q100 Triple 2-channel analog multiplexer/demultiplexer 6. Pinning information 6.1 Pinning Fig 4. Schematic diagram (one switch) 001aad544 from logic VCC VEE VEE VCC VCC VEE Y Z VCC (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to VCC. Fig 5. Pin configuration SO16 and TSSOP16 Fig 6. Pin configuration DHVQFN16 74HC4053-Q100 74HCT4053-Q100 2Y1 VCC 2Y0 2Z 3Y1 1Z 3Z 1Y1 3Y0 1Y0 ES1 VEE S2 GND S3 aaa-003164 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 aaa-003165 VEE S2 ES1 3Y0 1Y0 3Z 1Y1 3Y1 1Z 2Y0 2Z Transparent top view 7 10 6 11 5 12 4 13 3 14 2 15 terminal 1 index area VCC(1) 74HC4053-Q100 74HCT4053-Q100 |
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