SDR12872D1B62MT-60R datasheet(11/13 Pages) ETC2

Teilenummer	SDR12872D1B62MT-60R

Bauteilbeschribung	1GB DDR ??SDRAM registered DIMM

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Data Sheet

Rev.1.0

22.05.2008

Swissbit Germany AG

Wolfener Straße 36

Fon: +49 (0) 30 93 69 54 - 0

www.swissbit.com

Page 11

D-12681 Berlin

Fax: +49 (0) 30 93 69 54 - 55

eMail: info@swissbit.com

of 13

SERIAL PRESENCE-DETECT MATRIX

BYTE

DESCRIPTION

3200-3033

2700-2533

0

NUMBER OF SPD BYTES USED

0x80

1

TOTAL NUMBER OF BYTES IN SPD DEVICE

0x08

2

FUNDAMENTAL MEMORY TYPE

0x07

3

NUMBER OF ROW ADDRESSES ON ASSEMBLY

0x0d

4

NUMBER OF COLUMN ADDRESSES ON ASSEMBLY

0x0b

5

NUMBER OF PHYSICAL BANKS ON DIMM

0x02

6

MODULE DATA WIDTH

0x48

7

MODULE DATA WIDTH (continued)

0x00

8

MODULE VOLTAGE INTERFACE LEVELS (VDDQ)

0x04

9

SDRAM CYCLE TIME, (tCK )

(CAS LATENCY =2.5 (2700, 2100) ; CL=3* (3200)

0x50

0x60

10

SDRAM ACCESS FROM CLOCK, (tAC)

(CAS LATENCY =2.5 (2700, 2100); CL=3* (3200))

0x70

11

MODULE CONFIGURATION TYPE

0x02

12

REFRESH RATE/ TYPE

0x82

13

SDRAM DEVICE WIDTH (PRIMARY SDRAM)

0x08

14

ERROR- CHECKING SDRAM DATA WIDTH

0x08

15

MINIMUM CLOCK DELAY, BACK- TO- BACK

RANDOM COLUMN ACCESS

0x01

16

BURST LENGTHS SUPPORTED

0x0e

17

NUMBER OF BANKS ON SDRAM DEVICE

0x04

18

CAS LATENCIES SUPPORTED

0x1c

0x0c

19

CS LATENCY

0x01

20

WE LATENCY

0x02

21

SDRAM MODULE ATTRIBUTES

0x26

22

SDRAM DEVICE ATTRIBUTES: GENERAL

0xc0

23

SDRAM CYCLE TIME, (tCK)

(CAS LATENCY=2(2700, 2100) CL=2,5*(3200))

0x60

0x75

24

SDRAM ACCESS FROM CK, (tAC)

(CAS LATENCY=2(2700, 2100) CL=2.5*(3200)

0x70

25

SDRAM CYCLE TIME, (tCK)

(CAS LATENCY=1.5(2700, 2100) CL=2*(3200))

0x75

0x00

26

SDRAM ACCESS FROM CK, (tAC)

(CAS LATENCY=1.5(2700, 2100) CL=2*(3200)

0x75

0x00

27

MINIMUM ROW PRECHARGE TIME, (tRP)

0x3c

0x48

28

MINIMUM ROW ACTIVE TO ROW ACTIVE, (tRRD)

0x28

0x30

29

MINIMUM RAS# TO CAS# DELAY, (tRCD)

0x3c

0x48

30

MINIMUM RAS# PULSE WIDTH, (tRAS)

0x28

0x2a

31

MODULE BANK DENSITY

0x80

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