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SDU01G64H3BF2MT-50R Datenblatt(PDF) 7 Page - List of Unclassifed Manufacturers

Teilenummer SDU01G64H3BF2MT-50R
Bauteilbeschribung  1024MB DDR ??unbuffered DDR1 UDIMM
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SDU01G64H3BF2MT-50R Datenblatt(HTML) 7 Page - List of Unclassifed Manufacturers

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Data Sheet
Rev.1.1
09.01.2013
Swissbit AG
Industriestrasse 4
Fon: +41 (0) 71 913 03 03
www.swissbit.com
Page 7
CH-9552 Bronschhofen
Fax: +41 (0) 71 913 03 15
eMail: info@swissbit.com
of 13
IDD Specifications AND CONDITIONS
(0°C
≤ TA ≤ + 70°C ; VDDQ = +2.5V ± 0.2V, VDD = +2.5V ± 0.2V) see Note 1 on Page 9
Parameter
& Test Condition
Symb.
max.
3200-3033
2700-2533
Unit
OPERATING CURRENT *) : One device bank; Active-
Precharge;
tRC= tRC (Min); tCK = tCK (Min); DQ, DM and DQS inputs
changing
once per clock cycle; Address and control inputs
changing once every two clock cycles
IDDO
1280
1080
mA
OPERATING CURRENT :*)
One device bank; Active-Read-Precharge;
Burst = 2; tRC= tRC (Min);
tCK = tCK (Min);IOUT = 0mA;
Address and control inputs changing once per clock
cycle
IDD1
1920
1320
mA
PRECHARGE POWER-DOWN STANDBY CURRENT:
All device banks idle;
Power-down mode;
tCK = tCK (Min); CKE = (LOW)
IDD2P
80
80
mA
IDLE STANDBY CURRENT: CS# = HIGH; All device
banks idle;
tCK = tCK (Min); CKE= HIGH; Address and other control
inputs changing once per clock cycle.
VIN = VREF for DQ, DQS, and DM
IDD2F
880
720
mA
ACTIVE POWER-DOWN STANDBY CURRENT: One
device bank active; Power-down mode; tCK = tCK
(Min);CKE = LOW
IDD3P
720
560
mA
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE =
HIGH; One device bank; Active-Precharge; tRC= tRAS
(Max); tCK = tCK (Min); DQ, DM and DQS inputs
changing twice per clock cycle; Address and other
control inputs changing once per clock cycle
IDD3N
960
800
mA
OPERATING CURRENT:
Burst = 2; Reads; Continous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK = tCK (Min);
IOUT = 0mA
IDD4R
1560
1360
mA
OPERATING CURRENT: Burst = 2; Writes; Continuous
burst; One device bank active; Address and control
inputs changing once per clock cycle; tCK = tCK (Min);
DQ, DM, and DQS inputs changing twice per clock
cycle
IDD4W
1648
1440
mA
AUTO
REFRESH
CURRENT
tRC = tRC (Min)
IDD5
5520
4640
mA
tRC = 7.8125µs
IDD6
176
160
mA
SELF REFRESH CURRENT: CKE ≤ 0.2V
IDD7
80
80
mA
OPERATING CURRENT*): Four device bank interleaving
READs (BL =4) with auto precharge, tRC = tRC (Min);
tCK = tCK (Min); Address and control inputs change only during
Active READ, or WRITE commands
IDD8
3600
3280
mA
*) Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW)
mode.


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