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SDU01G64H3BJ2SA-50R Datenblatt(PDF) 2 Page - List of Unclassifed Manufacturers |
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SDU01G64H3BJ2SA-50R Datenblatt(HTML) 2 Page - List of Unclassifed Manufacturers |
2 / 13 page Data Sheet Rev.1.0 18.09.2012 Swissbit AG Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 2 CH-9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 13 This Swissbit module family is industry standard 184-pin 8-byte Double Date rate synchronous SDRAM Dual-In-line Memory Modules (DIMMs), which are organized as x64 high speed memory arrays designed for use in non-parity applications. DIMMs are assembled in TSOP Technology. The passive devices and the EEPROM are SMD components. The DIMM use serial presence detects (SPD) implemented via serial EEPROM using the two-pin-I 2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user. All Swissbit DIMMs provide a high performance, flexible 8-byte interface in a 133.35mm long footprint. All modules of the extended temperature grade have seen special tests during the manufacturing process to ensure proper operation according to the field of operation as stated in the environmental conditions. Module Configuration Organization DDR SDRAMs used Row Addr. Device Bank Addr. Column Addr. Refresh Module Bank Select 128M x 64bit 16 x 64M x 8bit (512Mbit) 13 BA0, BA1 11 8k S0#, S1# Module Dimensions in mm 133.35 (long) x 30(high) x 4.00 [max] (thickness) Product Parameters Part Number Module Density Transfer Rate Clock Cycle/Data bit rate Latency SDU01G64H3BJ2SA-50R 1024MB 3.2 GB/s 5.0ns/400MT/s 3.0-3-3 SDU01G64H3BJ2SA-60R 1024MB 2.7 GB/s 6.0ns/333MT/s 2.5-3-3 Pin Name A0 – A12 Address Inputs BA0, BA1 Bank Address Inputs DQ0 – DQ63 Data Input/Output DM0 – DM7 Input Data Mask RAS# Row Address Strobe CAS# Column Address Strobe WE# Read / Write Enable CKE0 – CKE1 Clock Enable CK0 – CK1 Clock Inputs, positive line CK0# – CK1# Clock Inputs, negative line DQS0 – DQS7 Data strobes |
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