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CS4226-BQ Datenblatt(PDF) 7 Page - Cirrus Logic |
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CS4226-BQ Datenblatt(HTML) 7 Page - Cirrus Logic |
7 / 60 page CS4226 DS188F1 7 SWITCHING CHARACTERISTICS - CONTROL PORT (T A = 25°C; VD+, VA+ = 5V ±5%; Inputs: logic 0 = DGND, logic 1 = VD+, CL = 30 pF) Notes: 12. I2C is a registered trademark of Philips Semiconductors. 13. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. S/PDIF RECEIVER CHARACTERISTICS (RX1, RX2, RX3, RX4 pins only; VD+, VA+ = 5V ±5%) Notes: 14. CLKOUT Jitter is for 256×FS selected as output frequency measured from falling edge to falling edge. Jitter is greater for 384×Fs and 512×Fs as selected output frequency. 15. For CLKOUT frequency equal to 1×Fs, 384×Fs, and 512×Fs. See Master Clock Output section. Parameter Symbol Min Max Units I2C® Mode (SPI/I2C = 1) (Note 12) SCL Clock Frequency fscl -100 kHz Bus Free Time Between Transmissions tbuf 4.7 µs Start Condition Hold Time (prior to first clock pulse) thdst 4.0 µs Clock Low Time tlow 4.7 µs Clock High Time thigh 4.0 µs Setup Time for Repeated Start Condition tsust 4.7 µs SDA Hold Time from SCL Falling (Note 13) thdd 0 µs SDA Setup Time to SCL Rising tsud 250 ns Rise Time of Both SDA and SCL Lines tr 1 µs Fall Time of Both SDA and SCL Lines tf 300 ns Setup Time for Stop Condition tsusp 4.7 µs Parameter Symbol Min Typ Max Units Input Resistance ZN -10- k Ω Input Voltage VTH 200 - - mVpp Input Hysteresis VHYST -50- mV Input Sample Frequency FS 30 - 50 kHz CLKOUT Jitter (Note 14) - 200 - ps RMS CLKOUT Duty Cycle (high time/cycle time) (Note 15) 40 50 60 % t buf t hdst t hdst t low t r t f t hdd t high t sud tsust t susp Stop Start Start Stop Repeated SDA SCL |
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Ähnliche Beschreibung - CS4226-BQ |
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