Datenblatt-Suchmaschine für elektronische Bauteile |
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CS4340A-KS Datenblatt(PDF) 10 Page - Cirrus Logic |
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CS4340A-KS Datenblatt(HTML) 10 Page - Cirrus Logic |
10 / 20 page CS4340A 10 DS590PP2 3.8 Mute Control The Mute Control pin goes high during power-up initialization, reset, or if the MCLK to LRCK ratio is incorrect. The pin will also go high following the reception of 8192 consecutive audio samples of static 0 or -1 on both the left and right channels. A single sample of non-zero data on either channel will cause the Mute Control pin to go low. This pin is intended to be used as a control for an external mute circuit to pre- vent the clicks and pops that can occur in any single-ended single supply system. Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system de- signer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute cir- cuit. See the CDB4340A data sheet for a suggested mute circuit. 3.9 Grounding and Power Supply Arrangements As with any high resolution converter, the CS4340A requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 1 shows the recommended power arrangements, with VA connected to a clean supply. If the ground planes are split between digital ground and analog ground, REF_GND & AGND should be connected to the analog ground plane. Decoupling capacitors should be as close to the DAC as possible, with the low value ceramic capacitor being the closest. To further minimize impedance, these capacitors should be located on the same layer as the DAC. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwant- ed coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path from FILT+ and REF_GND (as well as VQ and REF_GND), and should also be located on the same layer as the DAC. The CDB4340A evaluation board demonstrates the optimum layout and power supply arrangements. |
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