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CDB4360 Datenblatt(PDF) 10 Page - Cirrus Logic

Teilenummer CDB4360
Bauteilbeschribung  24-Bit, 192 kHz 6 Channel D/A Converter?
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Hersteller  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CDB4360 Datenblatt(HTML) 10 Page - Cirrus Logic

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CS4360
10
DS517PP1
SWITCHING CHARACTERISTICS- CONTROL PORT- TWO-WIRE FORMAT
(Note 16) (For -KS & -KZ parts TA = -10 to +70°C; for -BS & -BZ parts TA = -40 to +85°C; VLC = 1.7 V - 5.5 V;
Inputs: Logic 0 = GND, Logic 1 = VLC, CL =30pF)
Notes: 16. The Two-Wire Format is compatible with the I2C protocol.
17. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
18. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.
19.
for Single-Speed Mode,
for Double-Speed Mode,
for Quad-Speed Mode.
Parameter
Symbol
Min
Max
Unit
SCL Clock Frequency
fscl
-100
kHz
RST Rising Edge to Start
tirs
500
-
ns
Bus Free Time Between Transmissions
tbuf
4.7
-
µs
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
-
µs
Clock Low time
tlow
4.7
-
µs
Clock High Time
thigh
4.0
-
µs
Setup Time for Repeated Start Condition
tsust
4.7
-
µs
SDA Hold Time from SCL Falling
(Note 17)
thdd
0-
µs
SDA Setup time to SCL Rising
tsud
250
-
ns
Rise Time of SCL and SDA
trc, trc
-1
µs
Fall Time SCL and SDA
tfc, tfc
-300
ns
Setup Time for Stop Condition
tsusp
4.7
-
µs
Acknowledge Delay from SCL Falling
(Note 18)
tack
-
(Note 19)
ns
5
256
Fs
×
---------------------
5
128
Fs
×
---------------------
5
64
Fs
×
------------------
t
buf
t
hdst
t
lo w
t
hdd
t
high
t
sud
Stop
Sta rt
SD A
SCL
t
irs
RST
t
hdst
t
rc
t
fc
t sust
t susp
Sta rt
Stop
R epe ate d
t
rd
t
fd
t
ack
Figure 2. Control Port Timing - Two-Wire Format


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