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CS5317 Datenblatt(PDF) 10 Page - Cirrus Logic |
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CS5317 Datenblatt(HTML) 10 Page - Cirrus Logic |
10 / 32 page Decimation Aliasing effects due to decimation are identical in the CLKOR and CLKG1 modes. Aliasing is dif- ferent in the CLKG2 mode due to the difference in output sample rates (10 kHz vs. 20 kHz) and thus will be discussed separately. Aliasing in the CLKOR and CLKG1 Modes The delta-sigma modulator output is fed into the digital low-pass filter at the input sampling rate, fs in. The filter’s frequency response is shown in Figure 3. In the process of filtering the digitized signal the filter decimates the sampling rate by 128 (that is, fs out = fsin/128). In its most elemen- tary form, decimation simply involves ignoring - or selectively reading - a fraction of the available samples. In the process of decimation the output of the digital filter is effectively resampled at fs out, the output word rate, which has aliasing implications. Residual signals after filtering at multiples of fs out will alias into the baseband. For example, an in- put tone at 28 kHz will be attenuated by 39.9 dB. If fs out = 20 kHz, the residual tone will alias into the baseband and appear at 8 kHz in the output spectrum. If the input signal contains a large amount of out- of-band energy, additional analog and/or digital antialias filtering may be required. If digital post- filtering is used to augment the CS5317’s rejection above fs out/4 (that is, above 5 kHz), the filtering will also reject residual quantization noise from the modulator. This will typically in- crease the converter’s dynamic range to 88 dB. Further bandlimiting the digital output to fs out/8 (2.5 kHz at full speed) will typically increase dy- namic range to 90 dB. Aliasing in the CLKG2 Mode Aliasing effects in the CLKG2 mode can be mod- eled exactly as those in the CLKG1 mode with the output decimated by two (from 20 kHz to 10 kHz). This is most easily achieved by ignoring every other sample. In the CLKG2 mode the ratio of the output sampling rate to the filter’s -3 dB point is two, with no oversampling beyond the demands of the Nyquist criterion. Without the ability to roll-off substantially before fs out/2, the on-chip digital filter’s antialiasing value is dimin- ished. The CLKG2 mode should therefore be used only when the output data rate must be minimized due to communication and/or storage reasons. In ad- dition, adequate analog filtering must be provided prior to the A/D converter. Digital Design Considerations The CS5317 presents its 16-bit serial output MSB-first in 2’s complement format. The con- verter’s serial interface was designed to easily interface to a wide variety of micro’s and DSP’s. Appendix A offers several hardware interfaces to industry-standard processors. CLKOUT DATA 13 12 11 10 987 6 543 21 0 MSB (sign bit) LSB 15 14 15 14 f out DOUT Figure 4. Data Output CS5317 10 DS27F4 |
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