M-8880 datasheet(8/13 Pages) CLARE

Teilenummer	M-8880

Bauteilbeschribung	M-8880 DTMF Transceiver

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Hersteller	CLARE [Clare, Inc.]

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M-8880

40-406-00012, Rev. G

www.clare.com

Page 8

PARAMETER

SYMBOL

MIN

TYP*

MAX

UNITS

Receive signal conditions

Valid input signal levels

(each tone of composite signal; Notes 1, 2, 3, 5, 6, 9)

-29

27.5

—

+1

869

dBm

mVRMS

Positive twist accept (Notes 2, 3, 6, 9)

—

6

dB

Negative twist accept (Notes 2, 3, 6, 9)

—

6

dB

Frequency deviation accept (Notes 2, 3, 5, 9)

± 1.5% ± 2 Hz

—

Nom.

Frequency deviation reject (Notes 2, 3, 5)

± 3.5%

—

Nom.

Third tone tolerance (Notes 2, 3, 4, 5, 9, 10)

—

-16

—

dB

Noise tolerance (Notes 2, 3, 4, 5, 7, 9, 10)

—

-12

—

dB

Dial tone tolerance (Notes 2, 3, 4, 5, 8, 9, 11)

—

+22

—

dB

Call progress

Lower frequency (@ -25 dBm) accept

fLA

—

320

—

Hz

Upper frequency (@ -25 dBm) accept

fHA

—

510

—

Hz

Lower frequency (@ -25 dBm) reject

fLR

—

290

—

Hz

Upper frequency (@ -25 dBm) reject

fHR

—

540

—

Hz

Receive timing

Tone present detect time

tDP

5

11

14

ms

Tone absent detect time

tDA

0.5

4

8.5

ms

Tone duration accept (ref. Figure 12)

tREC

—

40

ms

Tone duration reject (ref. Figure 12)

tREC

20

—

ms

Interdigit pause accept (ref. Figure 12)

tID

—

40

ms

Interdigit pause reject (ref. Figure 12)

tDO

20

—

ms

Delay St to b3

tPStb3

—

13

—

µs

Delay St to RXO—RX3

tPStRX

—

8

—

µs

Transmit timing

Tone burst duration (DTMF mode)

tBST

50

—

52

ms

Tone pause duration (DTMF mode)

tPS

50

—

52

ms

Tone burst duration (extended, call progress mode)

tBSTE

100

—

104

ms

Tone pause duration (extended, call progress mode)

tPSE

100

—

104

ms

Tone output

High group output level (RL = 10 kΩ)

VHOUT

-6.1

—

-2.1

dBm

Low group output level (RL = 10 k

W)

VLOUT

-8.1

—

-4.1

dBm

Pre-emphasis (RL = 10 k

W)

dBP

0

2

3

dB

Output distortion (RL = 10 kΩ, 3.4 kHz bandwidth)

THD

—

-25

—

dB

Frequency deviation (f = 3.5795 MHz)

fD

—

± 0.7

± 1.5

%

Output load resistance

RLT

10

—

50

k

Ω

Microprocessor interface

φ 2 cycle period

tCYC

0.5

—

µs

φ2 high pulse width

tCH

200

—

ns

φ2 low pulse width

tCL

180

—

ns

φ2 rise and fall time

tR, tF

—

25

ns

Address, R/W hold time

tAH,tRWH

10

—

ns

Address, R/W setup time (prior to

φ2)

tAS, tRWS

23

—

ns

Table 12 AC Characteristics

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