Datenblatt-Suchmaschine für elektronische Bauteile |
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SI7005EVB-UDP-F960 Datenblatt(PDF) 5 Page - Silicon Laboratories |
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SI7005EVB-UDP-F960 Datenblatt(HTML) 5 Page - Silicon Laboratories |
5 / 41 page Si7005 Rev. 1.2 5 Power Consumption IDD RH conversion in progress — 240 560 µA Temperature conversion in progress — 320 565 µA Average for 1 temperature and 1 RH conversion / minute —1— µA CS < VIL; no conversion in progress; VDD = 3.3 V; SDA = SCL ≥ V IH — 150 — µA CS > VIH —— 100 µA CS < VIL; no conversion in progress; VDD = 3.3 V; SDA = SCL ≥ V IH; HEAT = 1 —24 31 mA Conversion Time tCONV 14-bit temperature; 12-bit RH (Fast = 0) 35 40 ms 13-bit temperature; 11-bit RH (Fast = 1) 18 21 Wake Up Time tCS From CS < VIL to ready for a temp/RH conversion 10 15 ms Power Up Time tPU From VDD ≥ 2.1V to ready for a temp/RH conversion 10 15 ms Table 2. General Specifications (Continued) 2.1 V DD 3.6 V; TA = 0 to 70 °C (F grade) or –40 to 85 °C (G grade) unless otherwise noted. Parameter Symbol Test Condition Min Typ Max Unit Notes: 1. Si7005 can draw excess current if VDD and CS are ramped high together. To enter the lowest power mode, either hold CS low while VDD ramps or pulse CS low after VDD reaches its final value. 2. SDA and SCL pins have an internal 75 k pull-up resistor to VDD |
Ähnliche Teilenummer - SI7005EVB-UDP-F960 |
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Ähnliche Beschreibung - SI7005EVB-UDP-F960 |
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