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ES1010SI 12V Hot-Swap Power Distribution Controllers

March 2014 Altera Corporation

that immediately shuts down the MOSFET switch should a rapid load current transient such as with a dead short cause the CR Vth to

exceed the programmed level by 150mV. Additionally, it has an UV indicator and an OC latch indicator. The functionality of the POK

feature is enabled once the IC is biased, monitoring and reporting any UV condition on the ISEN+ pin.

Upon initial power-up, the IC can either isolate the voltage supply from the load by holding the external N-Channel MOSFET

switch off or apply the supply rail voltage directly to the load for true hot swap capability. The EN pin must be pulled low for the

device to isolate the power supply from the load by holding the external N-Channel MOSFET off. With the EN pin held high or

floating the IC will be in true hot swap mode. In both cases the IC turns on in a soft-start mode protecting the supply rail from

sudden inrush current.

At turn-on, the external gate capacitor of the N-Channel MOSFET is charged with a 11µA current source resulting in a

programmable ramp (soft-start turn-on). The internal ES1010SI charge pump supplies the gate drive for the 12V supply switch

capacitor, on CLTIM pin is charged with a 20µA current source and the controller enters the current limit time to latch-off period. The

value and resulting nominal current limited time-out to latch-off duration placed from the CLTIM pin (pin 6) to ground. The

programmed current level is held until either the OC event passes or the time-out period expires. If the former is the case then the N-

period has expired, an internal latch is set whereby the FET gate is quickly pulled to 0V turning off the N-Channel MOSFET switch,

isolating the faulty load.

This IC responds to a severe overcurrent load (defined as a voltage across the sense resistor >150mV over the OC Vth set point) by

immediately driving the N-Channel MOSFET gate to 0V in about 10µs. The gate voltage is then slowly ramped up turning on the

N-Channel MOSFET to the programmed current regulation level; this is the start of the time-out period.

Upon a UV condition, the POK signal will pull low when connected through a resistor to the logic or VIN supply. This pin is a UV

fault indicator. For an OC latch-off indication, monitor CLTIM, pin 6. This pin will rise rapidly from 1.8V to VIN once the time-

out period expires.

See Figures 2 through 13 for graphs and waveforms related to text.

The IC is reset after an OC latch-off condition by a low level on the EN pin and is turned on by the EN pin being driven high.

Application Considerations

Design applications where the CR Vth is set extremely low (25mV or less), there is a two-fold risk to consider.

• There is the susceptibility to noise influencing the absolute CR Vth value. This can be addressed with a 100pF capacitor across the

• Due to common mode limitations of the overcurrent comparator, the voltage on the ISET- pin must be 20mV above the IC

may incorrectly report overcurrent fault at start-up when there is no fault. Circuits with high load capacitance and initially low

load current are susceptible to this type of unexpected behavior.

Do not signal nor pull-up the EN input to > 5V. Exceeding 6V on this pin will cause the internal charge pump to malfunction.

NOMINAL CR VTH

10k



200mV

4.99k



100mV

2.5k



50mV

1.25k



25mV

0.022µF

2ms

0.047µF

4.4ms

0.1µF

9.3ms

09617

March 14, 2014

Rev A