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CDCM6208 Datenblatt(PDF) 3 Page - Texas Instruments |
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CDCM6208 Datenblatt(HTML) 3 Page - Texas Instruments |
3 / 89 page CDCM6208 www.ti.com SCAS931F – MAY 2012 – REVISED APRIL 2014 Changes from Revision C (September 2012) to Revision D Page • Changed the Description of pin VDD_PRI_REF .................................................................................................................... 4 • Changed the Description of pin VDD_SEC_REF ................................................................................................................... 4 • Changed Figure 35 ............................................................................................................................................................... 33 • Changed Table 6 - Note 2 and row 10 - 0x1C, PinMode 29-V1, fout(Y7) From: 33.33 To: 44.44....................................... 36 • Changed Table 7 - Note 2 and row 10 - 0x13, PinMode 20-V2, fout(Y7) From: 25 To: 12.5 .............................................. 38 • Changed text in the PLL lock detect section From: "1/1000 th of the input reference frequency" To: "1/1000 th of the PFD update frequency" ........................................................................................................................................................ 42 • Changed text in the PLL lock detect section From: "approximately 1000 input clock cycles" To: "approximately 1000 PFD update clock cycles" ..................................................................................................................................................... 42 • Changed Figure 60, From: PDN held Low To: RESETN held low ....................................................................................... 72 • Changed Equation 4 ............................................................................................................................................................. 74 Changes from Revision B (August 2012) to Revision C Page • Changed Table 37, 2:0 DIE_REVISION Description............................................................................................................ 60 • Added text "Example: SERDES link with KeyStone™ I DSP" ............................................................................................. 62 Changes from Revision A (June 2012) to Revision B Page • Editorial changes made throughout the data sheet................................................................................................................ 1 • Changed the Description of pin VDD_PRI_REF .................................................................................................................... 4 • Changed the Description of pin VDD_SEC_REF ................................................................................................................... 4 • Added Table Note 1 to the description of pin 44. ................................................................................................................... 6 • Added Note to the Preventing false output frequencies in SPI/I2C mode at startup: section.............................................. 34 • Changed the NOTE following Table 10................................................................................................................................ 42 • Added Note to the I 2C SERIAL INTERFACE section........................................................................................................... 46 • Deleted text "All outputs PECL (Y4:0) and LVDS (Y7:4)." from the Conclusion statement ................................................. 65 • Changed the text in the OUTPUT MUX on Y4 and Y5 section............................................................................................ 69 • Changed the text in item 1 of the Staggered CLK output powerup for power sequencing of a DSP section...................... 69 • Changed the first paragraph in the Power Down section..................................................................................................... 74 • Changed the first paragraph in the Power Supply Ripple Rejection (PSRR) versus Ripple Frequency section ................. 74 Changes from Original (May 2012) to Revision A Page • Changed the device From: Product Preview To: Production ................................................................................................. 1 • Section Header From: RESTN, PWR, SYNC To: RESETN, PWR, SYNCN, PDN, REF_SEL, SI_MODE[1:0]..................... 9 • Changed the RPULLUP parametres From: RPULLUP - Input Pullup Resistor To: R - Input Pullup and Pulldown Resistor ......... 9 Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: CDCM6208 |
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