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L6393D Datenblatt(PDF) 4 Page - STMicroelectronics |
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4 / 19 page Pin connection L6393 4/19 Doc ID 14497 Rev 4 2 Pin connection Figure 2. Pin connection (top view) Table 2. Pin description Pin N# Pin name Type Function 1 PHASE I Driver logic input (active high) 2 SD (1) 1. The circuit provides less than 1 V on the LVG and HVG pins (@ Isink = 10 mA), with VCC > 3 V. This allows omitting the “bleeder” resistor connected between the gate and the source of the external MOSFET normally used to hold the pin low; the gate driver assures low impedance also in SD condition. I Shut down input (active low) 3 BRAKE I Driver logic input (active low) 4 VCC P Lower section supply voltage 5 DT I Dead time setting 6 CPOUT O Comparator output (open drain) 7 GND P Ground 8 CP- I Comparator negative input 9 CP+ I Comparator positive input 10 LVG (1) O Low side driver output 11 NC Not connected 12 OUT P High side (floating) common voltage 13 HVG (1) O High side driver output 14 BOOT P Bootstrapped supply voltage |
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