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TPD4S009 Datenblatt(PDF) 2 Page - Texas Instruments |
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TPD4S009 Datenblatt(HTML) 2 Page - Texas Instruments |
2 / 20 page D1+ D1– GND D2+ D2– D1+ D1– GND V CC D2+ D2– TPD4S009 TPD4S010 SLVS817F – MAY 2008 – REVISED AUGUST 2013 www.ti.com CIRCUIT DIAGRAMS Figure 1. TPD4S009 Figure 2. TPD4S010 TERMINAL FUNCTIONS DBV, DCK, DGS DQA OR DRY NAME I/O DESCRIPTION PIN NO. PIN NO. PIN NO. 1, 6, 1, 2, 1, 2, D1+, D1–, High-speed ESD clamp provides ESD protection to the high- ESD port 3, 4 4, 5 4, 5 D2+, D2– speed differential data lines. 2 3 3, 8 GND GND Ground – 6, 7, 9, 10 6, 7, 9, 10 N.C. – Not internally connected 5 8 – VCC Power Supply 2 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: TPD4S009 TPD4S010 |
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Ähnliche Beschreibung - TPD4S009_14 |
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