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ADS8512IBDW Datenblatt(PDF) 5 Page - Texas Instruments |
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ADS8512IBDW Datenblatt(HTML) 5 Page - Texas Instruments |
5 / 34 page PIN CONFIGURATION V S BUSY CS DATACLK R1 IN GND BUF CAP 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 R2 IN REF EXT/INT DATA PWRD R3 IN GND CONV ADS8512 www.ti.com ...................................................................................................................................................................................................... SLAS485 – JUNE 2008 DW PACKAGE SO-16 (TOP VIEW) Terminal Functions TERMINAL DIGITAL NAME NO. I/O DESCRIPTION R1IN 1 Analog input. See Table 1 and Table 3. R2IN 3 Analog input. See Table 1 and Table 3. R3IN 4 Analog input. See Table 1 and Table 3. BUF 5 Reference buffer output. Connect to R1IN, R2IN, or R3IN as needed. Reference buffer compensation node. Decouple to ground with a 1- µF tantalum capacitor in CAP 6 parallel with a 0.01- µF ceramic capacitor. Reference input/output. Outputs internal 2.5-V reference via a series 4-k Ω resisitor. Decouple this REF 7 voltage with a 1- µF to 2.2-µF tantalum capacitor to ground. If an external reference voltage is applied to this pin, it overrides the internal reference. Data clock pin. With EXT/INT low, this pin is an output and provides the synchrnous clock for the DATACLK 9 I/O serial data. The output is 3-stated when CS is high. With EXT/INT high, this pin is an input and the serial data clock must be provided externally. Serial data output. The serial data are always the result of the last completed conversion and are DATA 10 O synchronized to DATACLK. If DATACLK is from the internal clock (EXT/INT low), the serial data are valid on both the rising and falling edges of DATACLK. DATA is 3-stated when CS is high. External/Internal DATACLK pin. Selects the source of the synchronous clock for serial data. if high, the clock must be provided externally. If low, the clock is derived from the internal conversion EXT/INT 11 I clock. Note that the clock used to time the conversion is always interna,l regardless of the status of EXT/INT. Convert input. A falling edge on this input puts the internal sample/hold into the hold state and starts a conversion regardless of the state of CS. If a conversion is already in progress, the falling CONV 12 edge is ignored. If EXT/INT is low, data from the previous conversion will be serially transmitted during the current conversion. Chip select. This input 3-states all outputs when high, and enables all outputs when low, including CS 13 I DATA, BUSY, and DATACLK (when EXT/INT is low). Note that a falling edge on CONV will initiate a conversion even when CS is high. Busy output. When a conversion starts, BUSY goes low and remains low throughout the BUSY 14 O conversion. If EXT/INT is low, data are serially transmitted while BUSY is low. BUSY is 3-stated when CS is high. Power down input. When high, the majority of the ADS8512 is placed in a low-power mode, and power consumption is significantly reduced. CONV must be taken low before PWRD goes in order PWRD 15 I to achieve the lowest power consumption. The time required for the ADS8512 to return to normal operation after power down depends on a number of factors. Consult the Power-Down section for more information. GND 2, 8 Ground. +5-V supply input. For best performance, decouple to ground with a 0.1- µF ceramic capacitor in VS 16 parallel with a 10- µF tantalum capacitor. Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): ADS8512 |
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