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ADS8513IDWRG4 Datenblatt(PDF) 5 Page - Texas Instruments |
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ADS8513IDWRG4 Datenblatt(HTML) 5 Page - Texas Instruments |
5 / 34 page PIN CONFIGURATION VS BUSY CS DATACLK R1IN GND BUF CAP 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 R2IN REF EXT/INT DATA PWRD R3IN GND CONV ADS8513 www.ti.com ...................................................................................................................................................... SLAS486C – JUNE 2007 – REVISED JANUARY 2009 DW PACKAGE SO-16 (TOP VIEW) Pin Assignments PIN DIGITAL NAME NO. I/O DESCRIPTION R1IN 1 Analog input. See Table 1 and Table 3. R2IN 3 Analog input. See Table 1 and Table 3. R3IN 4 Analog input. See Table 1 and Table 3. BUF 5 Reference buffer output. Connect to R1IN, R2IN, or R3IN as needed 6 Reference buffer compensation node. Decouple to ground with a 1- µF tantalum capacitor in parallel CAP with a 0.01 µF ceramic capacitor. 7 Reference input/output. Outputs internal 2.5V reference via a series 4k Ω resistor. Decouple this REF voltage with a 1 µF to 2.2µF tantalum capacitor to ground. If an external reference voltage is applied to this pin, it overrides the internal reference. 9 I/O Data clock pin. With EXT/INT low, this pin is an output and provides the synchronous clock for the DATACLK serial data. The output is 3-stated when CS is high. With EXT/INT high, this pin is an input and the serial data clock must be provided externally. 10 O Serial data output. The serial data are always the result of the last completed conversion and are DATA synchronized to DATACLK. If DATACLK is from the internal clock (EXT/INT low), the serial data are valid on both the rising and falling edges of DATACLK. DATA is 3-stated when CS is high. 11 I External/Internal DATACLK pin. Selects the source of the synchronous clock for serial data. If high, the clock must be provided externally. If low, the clock is derived from the internal conversion clock. EXT/INT Note that the clock used to time the conversion is always interna,l regardless of the status of EXT/INT. 12 Convert input. A falling edge on this input puts the internal sample/hold into the hold state and starts a conversion regardless of the state of CS. If a conversion is already in progress, the falling edge is CONV ignored. If EXT/INT is low, data from the previous conversion are serially transmitted during the current conversion. 13 I Chip select. This input 3-states all outputs when high and enables all outputs when low, including CS DATA, BUSY, and DATACLK (when EXT/INT is low). Note that a falling edge on CONV initiates a conversion even when CS is high. 14 O Busy output. When a conversion starts, BUSY goes low and remains low throughout the conversion. BUSY If EXT/INT is low, data are serially transmitted while BUSY is low. BUSY is 3-stated when CS is high. 15 I Power-down input. When high, the majority of the ADS8513 circuitry is placed in a low-power mode and power consumption is significantly reduced. (The ADS7813 requires CONV be taken low before PWRD goes low in order to achieve the lowest power consumption. This is not necessary for the PWRD ADS8513 and it does not cause interference if performed.) The time required for the ADS7813 to return to normal operation after power down depends on a number of factors. Consult the Chapter 0 section for more information. GND 2, 8 Ground. 16 +5V supply input. For best performance, decouple to ground with a 0.1 µF ceramic capacitor in VS parallel with a 10 µF tantalum capacitor. Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): ADS8513 |
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Ähnliche Beschreibung - ADS8513IDWRG4 |
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