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HD74AC174 Datenblatt(PDF) 2 Page - Hitachi Semiconductor |
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HD74AC174 Datenblatt(HTML) 2 Page - Hitachi Semiconductor |
2 / 9 page HD74AC174 2 Logic Symbol D0 D1 D2 D3 D4 D5 Q0 CP MR Q1 Q2 Q3 Q4 Q5 Pin Names D 0 to D5 Data Inputs CP Clock Pulse Input MR Master Reset Input Q 0 to Q5 Outputs Functional Description The HD74AC174 consists of six edge-triggered D flip-flops with individual D inputs and Q outputs. The Clock (CP) and Master Reset ( MR) are common to all flip-flops. Each D input’s state is transferred to the corresponding flip-flops’s output following the Low-to-High Clock (CP) transition. A Low input to the Master Reset ( MR) will force all outputs Low independent of Clock or Data inputs. The HD74AC174 is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. Truth Table Inputs Output MR CP D Q LX X L H HH H LL H LXQ H : High Voltage Level L : Low Voltage Level X : Immaterial : Low-to-High Transition of Clock |
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