HD74AC174

2

Logic Symbol

CP

MR

Pin Names

D

Data Inputs

CP

Clock Pulse Input

MR

Master Reset Input

Q

Outputs

Functional Description

The HD74AC174 consists of six edge-triggered D flip-flops with individual D inputs and Q outputs. The

Clock (CP) and Master Reset (

MR) are common to all flip-flops. Each D input’s state is transferred to the

corresponding flip-flops’s output following the Low-to-High Clock (CP) transition. A Low input to the

Master Reset (

MR) will force all outputs Low independent of Clock or Data inputs. The HD74AC174 is

useful for applications where the true output only is required and the Clock and Master Reset are common

to all storage elements.

Truth Table

Inputs

Output

MR

CP

D

Q

LX

X

L

H

HH

H

LL

H

LXQ

H :

High Voltage Level

L

:

Low Voltage Level

X :

Immaterial

:

Low-to-High Transition of Clock