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HCPL-5301-300 Datenblatt(PDF) 7 Page - Agilent(Hewlett-Packard)

Teilenummer HCPL-5301-300
Bauteilbeschribung  Intelligent Power Module and Gate Drive Interface Hermetically Sealed Optocouplers
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Hersteller  HP [Agilent(Hewlett-Packard)]
Direct Link  http://www.home.agilent.com
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7
Switching Specifications (RL= Internal Pull-up)
Over recommended operating conditions:
(TA = -55°C to +125°C, VCC = +4.5 V to 30 V, IF(ON) = 10 mA to 20 mA, VF(OFF) = -5 V to 0.8 V) unless
otherwise specified.
Group A
Parameter
Symbol Subgrps.[12] Min. Typ.* Max. Units
Test Conditions
Fig.
Note
Propagation
tPHL
9, 10, 11
20
185
500
ns
IF(on) = 10 mA,
5, 8,
3, 4,
Delay Time to
VF(off) = 0.8 V,
5, 6,
Low Output
VCC = 15.0 V,
7
Level
CL = 100 pF,
Propagation
tPLH
9, 10, 11
220
415
750
ns
Delay Time to
High Output
Level
Pulse Width
PWD
9, 10, 11
150
600
ns
11
Distortion
Propagation
tPLH -
9, 10, 11
-225
150
650
ns
8
Delay
tPHL
Difference
Between Any
Two Parts
Output High
|CMH|10
kV/
µsI
F = 0 mA,
VCC = 15.0 V,
6, 21
9
Level Common
VO > 3.0 V CL = 100 pF,
Mode Transient
VCM = 1000
Immunity
T
A = 25°C
Output Low
|CM
L|10
kV/
µsI
F = 16 mA
10
Level Common
V
O < 1.0 V
Mode Transient
Immunity
Power Supply
PSR
1.0
V
P-P
Square Wave, t
RISE, tFALL
7
Rejection
> 5 ns, no bypass
capacitors.
*All typical values at 25
°C, V
CC = 15 V.
Notes:
1. CURRENT TRANSFER RATIO in percent is defined as the ratio of output collector current (IO) to the forward LED input current
(IF) times 100.
2. Device considered a two-terminal device: Pins 1, 2, 3 and 4 shorted together and Pins 5, 6, 7 and 8 shorted together.
3. Pulse: f = 20 kHz, Duty Cycle = 10%
4. The internal 20 k
Ω resistor can be used by shorting pins 6 and 7 together.
5. Due to the tolerance of the internal resistor, and since propagation delay is dependent on the load resistor value, performance can
be improved by using an external 20 k
Ω 1% load resistor. For more information on how propagation delay varies with load
resistance, see Figure 8.
6. The RL = 20 kΩ, CL = 100 pF represents a typical IPM (Intelligent Power Module) load.
7. Use of a 0.1
µF bypass capacitor connected between pins 5 and 8 can improve performance by filtering power supply line noise.
8. The difference in tPLH and tPHL between any two parts under the same test condition. (See IPM Dead Time and Propagation Delay
Specifications section.)
9. Common mode transient immunity in a Logic High level is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to
assure that the output will remain in a Logic High state (i.e., VO > 3.0 V).
10. Common mode transient immunity in a Logic Low level is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to
assure that the output will remain in a Logic Low state (i.e., VO < 1.0 V).
11. Pulse Width Distortion (PWD) is defined as the difference between tPLH and tPHL for any given device.
12. Standard parts receive 100% testing at 25
°C (Subgroups 1 and 9). Hi-Rel and SMD parts receive 100% testing at 25°C, +125°C,
and -55
°C (Subgroups 1 and 9, 2 and 10, 3 and 11 respectively).
13. Parameters are tested as part of device initial characterization and after design and process changes. Parameters are guaranteed
to limits specified for all lots not specifically tested.
VTHLH = 2.0 V
VTHHL = 1.5 V


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