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74LVC1G11GN Datenblatt(PDF) 1 Page - NXP Semiconductors |
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74LVC1G11GN Datenblatt(HTML) 1 Page - NXP Semiconductors |
1 / 17 page 1. General description The 74LVC1G11 provides a single 3-input AND gate. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. Schmitt-trigger action at all inputs makes the circuit highly tolerant to slower input rise and fall time. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features and benefits Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant inputs for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) 24 mA output drive (V CC =3.0 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Multiple package options Specified from 40 Cto+85 C and 40 Cto+125 C 74LVC1G11 Single 3-input AND gate Rev. 7 — 4 July 2012 Product data sheet |
Ähnliche Teilenummer - 74LVC1G11GN |
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Ähnliche Beschreibung - 74LVC1G11GN |
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