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AD1855 Datenblatt(PDF) 6 Page - Analog Devices

Teilenummer AD1855
Bauteilbeschribung  Stereo, 96 kHz, Multibit DAC
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Hersteller  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

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AD1855
REV. B
–6–
OPERATING FEATURES
Serial Data Input Port
The AD1855’s flexible serial data input port accepts data in
twos-complement, MSB-first format. The left channel data field
always precedes the right channel data field. The input data
consists of either 16, 18, 20 or 24 bits, as established by the
mode select pins (IDPM0 Pin 21 and IDPM1 Pin 20) or the
mode select bits (Data 15 and 14) in the control register
through the SPI (Serial Peripheral Interface) control port. Nei-
ther the pins nor the SPI controls has preference; to ensure
proper control the selection not being used should be tied LO.
Therefore, when the SPI bits are used to control Serial Data
Input Format, Pins 20 and 21 should be tied LO. Similarly,
when the Pins are to be used to select the Data Format, the SPI
bits should be set to Zeros. When the SPI Control Port is not
being used, the SPI Pins (3, 4 and 5) should be tied LO.
Serial Data Input Mode
The AD1855 uses two multiplexed input pins to control the
mode configuration of the input data port mode as follows:
Table I. Serial Data Input Modes
IDPM1
IDPM0
(Pin 20)
(Pin 21)
Serial Data Input Format
0
0
Right Justified (16 Bits Only)
01
I
2S-Compatible
1
0
Left Justified
1
1
DSP
Figure 1 shows the right-justified mode. L/
RCLK is HI for the
left channel, LO for the right channel. Data is valid on the
rising edge of BCLK. The MSB is delayed 16 bit clock periods
from an L/
RCLK transition, so that when there are 64 BCLK
periods per L/
RCLK period, the LSB of the data will be right
justified to the next L/
RCLK transition. The right-justified
mode can only be used with 16-bit inputs.
Figure 2 shows the I
2S-justified mode. L/
RCLK is LO for the
left channel and HI for the right channel. Data is valid on the
rising edge of BCLK. The MSB is left justified to an L/
RCLK
transition but with a single BCLK period delay. The I
2S-justified
mode can be used with 16-/18-/20- or 24-bit inputs.
Figure 3 shows the left-justified mode. L/
RCLK is HI for the
left channel, and LO for the right channel. Data is valid on the
rising edge of BLCK. The MSB is left justified to an L/
RCLK
transition, with no MSB delay. The left-justified mode can be
used with 16-/18-/20- or 24-bit inputs.
Figure 4 shows the left-justified DSP serial port style mode.
L/
RCLK must pulse HI for at least one bit clock period before
the MSB of the left channel is valid, and L/
RCLK must pulse
HI again for at least one bit clock period before the MSB of the
right channel is valid. Data is valid on the falling edge of BCLK.
The left-justified DSP serial port style mode can be used with
16-/18-/20- or 24-bit inputs.
Note that in this mode, it is the responsibility of the DSP to
ensure that the left data is transmitted with the first L/
RCLK
pulse, and that synchronism is maintained from that point
forward.
The AD1855 is capable of a 32
× FS BCLK frequency “packed
mode” where the MSB is left justified to an L/
RCLK transition,
and the LSB is right justified to an L/
RCLK transition. L/RCLK
is HI for the left channel and LO for the right channel. Data is
valid on the rising edge of BLCK. Packed mode can be used
when the AD1855 is programmed in right- or left-justified
mode. Packed mode is shown is Figure 5.
Table II. Frequency Mode Settings
FS
96/
48
MCLK
X2MCLK
384/
256
Note
8
× Interpolation Mode
Normal, 32 kHz–48 kHz
0
256
× F
S
00
0
384
× FS
01
0
512
× FS
10
0
1
1
Not Allowed
4
× Interpolation Mode
Double FS (96 kHz)
1
128
× FS
00
1
(384/2)
× FS
01
1
256
× F
S
10
1
1
1
Not Allowed


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