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MC146805E2FN Datenblatt(PDF) 4 Page - InnovASIC, Inc |
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MC146805E2FN Datenblatt(HTML) 4 Page - InnovASIC, Inc |
4 / 31 page IA6805E2 Data Sheet Microprocessor Unit As of Production Version 00 Copyright © 2002 ENG21108140100 www.innovasic.com innovASIC Customer Support: The End of Obsolescence ™ Page 4 of 31 1-888-824-4184 I/O Port Circuitry and Register Configuration: I/O Pin Functions R/W-n DDR I/O Pin Functions 0 0 The I/O pin is in input mode. Data is written into the output data latch. 0 1 Data is written into the output data latch and output to the I/O pin. 1 0 The state of the I/O pin is read. 1 1 the I/O pin is in an output mode. The output data latch is read. DATA DIRECTION REGISTER BIT I/O PIN OUTPUT LATCHED OUTPUT DATA BIT INPUT REG BIT INPUT I/O PIN TO AND FROM CPU DDA7 (DDB7) DDA1 (DDB1) DDA2 (DDB2) DDA3 (DDB3) DDA4 (DDB4) DDA5 (DDB5) DDA6 (DDB6) DDA0 (DDB0) DATA DIRECTION A(B) REGISTER PORT A(B) REGISTER 7 4 5 6 3 0 1 2 PA7 (PB7) PA6 (PB6) PA5 (PB5) PA4 (PB4) PA3 (PB3) PA2 (PB2) PA1 (PB1) PA0 (PB0) PIN $0004 ($0005) $0000 ($0001) Figure 2. PA0 -PA7/PB0-PB7 (Input/Output Lines) |
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