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AD5452YUJZ-REEL Datenblatt(PDF) 5 Page - Analog Devices

Teilenummer AD5452YUJZ-REEL
Bauteilbeschribung  8-/10-/12-/14-Bit High Bandwidth Multiplying DACs with Serial Interface
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Direct Link  http://www.analog.com
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Data Sheet
AD5450/AD5451/AD5452/AD5453
Rev. G | Page 5 of 28
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V,
VREF = 10 V, temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1
VDD = 2.5 V to 5.5 V
Unit
Description
fSCLK
50
MHz max
Maximum clock frequency
t1
20
ns min
SCLK cycle time
t2
8
ns min
SCLK high time
t3
8
ns min
SCLK low time
t4
8
ns min
SYNC falling edge to SCLK active edge setup time
t5
5
ns min
Data setup time
t6
4.5
ns min
Data hold time
t7
5
ns min
SYNC rising edge to SCLK active edge
t8
30
ns min
Minimum SYNC high time
Update Rate
2.7
MSPS
Consists of cycle time, SYNC high time, data setup, and
output voltage settling time
1
Guaranteed by design and characterization, not subject to production test.
SCLK
SYNC
DIN
DB15
DB0
t7
t3
t2
t6
t5
t4
t8
t1
Figure 2. Timing Diagram


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