ISL54233

6

FN7918.0

December 21, 2011

Test Circuits and Waveforms

Logic input waveform is inverted for switches that have the opposite logic

sense.

capacitance.

FIGURE 3. SWITCHING TIMES

FIGURE 4A. MEASUREMENT POINTS

FIGURE 4B. TEST CIRCUIT

FIGURE 4. BREAK-BEFORE-MAKE TIME

FIGURE 6. CAPACITANCE TEST CIRCUIT

50%

90%

0V

LOGIC

INPUT

SWITCH

INPUT

SWITCH

OUTPUT

90%

V

OUT

V

(INPUT)

R

L

R

L

r

ON

+

------------------------

=

SWITCH

INPUT

LOGIC

COMx

C0, C1

50

Ω

10pF

GND

C

INPUT

90%

LOGIC

INPUT

SWITCH

OUTPUT

0V

LOGIC

C0, C1

COMx

10pF

50

Ω

2D- OR 2D+

1D- OR 1D+

GND

C

INPUT

3D- OR 3D+

C

0V

xD- OR xD+

COMx

C0

GND

17mA

Repeat test for all switches.

C1

C

GND

xD- OR xD+

COMx

IMPEDANCE

ANALYZER

Repeat test for all switches.

CTRL