Datenblatt-Suchmaschine für elektronische Bauteile |
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L6521TR Datenblatt(PDF) 10 Page - STMicroelectronics |
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L6521TR Datenblatt(HTML) 10 Page - STMicroelectronics |
10 / 19 page Functions description L6520, L6521 10/19 Doc ID 16998 Rev 3 5.3 Ignition During the ignition sequence the output frequency ramps down from the programmed preheating frequency to the fixed run frequency with a fixed rate dfIGN/dt of - 2.75 kHz/ms. If the instant start is selected, the frequency ramps down from 85 kHz to 46.6 kHz (typ.) with the same rate. The current control circuit limits the maximum lamp voltage (OCPH) in case of old or broken lamp and it is able to control the lamp current in case of inductor saturation (CSC). The ignition phase lasts for maximum 200 ms. If the Run frequency is not reached during ignition phase, the IC is turned off (latched). 5.4 Run mode The run frequency is internally set to 46.6 kHz. The HSD and LSD pins drive respectively the high side and the low side switches. The potential isolation to the high side switch is realized by a pulse transformer. The HSD and LSD drivers are able to manage the inductive load represented by the primary side of the pulse transformer. Between the turn-off of one driver and turn-on of the other one there is a dead time automatically optimized accordingly to the kind of the half bridge switches (MOS or BJT) to ensure the maximum reliability. The CCC protects the circuit against over currents, choke saturation and hard switching events. 5.5 Storage time compensation network In all the operating states (preheating, ignition and run mode), the storage time compensation ensures the application of the fixed dead time (tDEAD, 1.42 us typ.) once the BJT's collector current is effectively reduced to zero. The tDEAD is the sum of a fixed time, generated by internal logic and the propagation delay of PWM_det comparator. The voltage level of the middle point of the half bridge is monitored through the PWM_det pin: the high side switch is turned on after a fixed dead time from the instant when the voltage on the PWM_det pin is above 2.65 V. The time between the falling edge of pin LSD and the rising edge of HSD is recorded in order to set the same dead time between the falling edge of pin HSD and the rising edge of pin LSD. The minimum duration of the resulting ON time is internally limited to 1 µs. This condition can last for a maximum time equal to 200 ms. After this time the IC is shut down (latched). The PWM_det pin embeds a 5 V (typ.) clamping zener, allowing the connection between the half bridge middle point and the pin itself by means of a limiting resistor. When driving MOSFET no storage time is present, therefore the resulting dead time is equal to (1.42 µs). |
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