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CA3338AM Datenblatt(PDF) 4 Page - Intersil Corporation

Teilenummer CA3338AM
Bauteilbeschribung  CMOS Video Speed, 8-Bit, 50 MSPS, R2R D/A Converters
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Hersteller  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

CA3338AM Datenblatt(HTML) 4 Page - Intersil Corporation

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10-14
Digital Signal Path
The digital inputs (LE, COMP, and D0 - D7) are of TTL
compatible HCT High Speed CMOS design: the loading is
essentially capacitive and the logic threshold is typically
1.5V.
The 8 data bits, D0 (weighted 20) through D7 (weighted 27),
are applied to Exclusive OR gates (see Functional Diagram).
The COMP (data complement) control provides the second
input to the gates: if COMP is high, the data bits will be
inverted as they pass through.
The input data and the LE (latch enable) signals are next
applied to a level shifter. The inputs, operating between the
levels of VDD and VSS, are shifted to operate between VDD
and VEE. VEE optionally at ground or at a negative voltage,
will be discussed under bipolar operation. All further logic
elements except the output drivers operate from the VDD
and VEE supplies.
The upper 3 bits of data, D5 through D7, are input to a 3-to-7
line bar graph encoder. The encoder outputs and D0 through
D4 are applied to a feedthrough latch, which is controlled by
LE (latch enable).
REFERENCE VOLTAGE
VREF+ Range
(+) Full Scale, Note 1
VREF- + 3
-
VDD
V
VREF- Range
(-) Full Scale, Note 1
VEE
-VREF+ - 3
V
VREF+ Input Current
VREF+ = 6V, VDD = 6V
-
40
50
mA
SUPPLY VOLTAGE
Static IDD or IEE
LE = Low, D0 - D7 = High
-
100
220
µA
LE = Low, D0 - D7 = Low
-
-
100
µA
Dynamic IDD or IEE
VOUT = 10MHz, 0V to 5V Square Wave
-
20
-
mA
Dynamic IDD or IEE
VOUT = 10MHz, ±2.5V Square Wave
-
25
-
mA
VDD Rejection
50kHz Sine Wave Applied
-
3
-
mV/V
VEE Rejection
50kHz Sine Wave Applied
-
1
-
mV/V
DIGITAL INPUTS
D0 - D7, LE, COMP
High Level Input Voltage
Note 1
2
-
-
V
Low Level Input Voltage
Note 1
-
-
0.8
V
Leakage Current
-
±1
±5
µA
Capacitance
-
5
-
pF
TEMPERATURE COEFFICIENTS
Output Impedance
-
200
-
ppm/oC
NOTE:
1. Parameter not tested. but guaranteed by design or characterization.
Electrical Specifications TA = 25oC, VDD = 5V, VREF+ = 4.608V, VSS = VEE = VREF- = GND, LE Clocked at 20MHz, RL ≥ 1 MΩ,
Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Pin Descriptions
PIN
NAME
DESCRIPTION
1
D7
Most Significant Bit
2
D6
Input
3
D5
Data
4
D4
Bits
5
D3
(High = True)
6D2
7D1
8VSS
Digital Ground
9D
0
Least Significant Bit. Input Data Bit
10
VEE
Analog Ground
11
VREF- Reference Voltage Negative Input
12
VOUT
Analog Output
13
VREF+ Reference Voltage Positive Input
14
COMP
Data Complement Control input. Active High
15
LE
Latch Enable Input. Active Low
16
V
DD
Digital Power Supply, +5V
CA3338, CA3338A


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